//    Synchronization timers
//    Don't use asynchronous "dev_clrn" signal with external superviser

    reg    clear_event;
    initial clear_event = 1'b 1;

    always @( posedge clock ) clear_event <= 1'b 0;

// Synchronization timers
// Don't use asynchronous "dev_clrn" signal with external superviser

reg clear_event = 1'b 1;

always @( posedge clock ) clear_event <= 1'b 0;

// Autoreload timer ( 1 ms )

wire sample_1ms;

timer_n #( .NBITS ( 15 ), .NTICKS ( 24_999 ) )
u25 (
.clock ( clock ),
.clear ( 1'b 0 ),
.load ( sample_1ms | clear_event ),
.count ( 1'b 1 ),
.done ( sample_1ms )
);

// Global clear trigger and interval timer ( 100 ms )

wire clear_done;
reg clear;

always @( posedge clock, posedge clear_event )

if ( clear_event ) clear <= 1'b 1;
else if ( clear_done ) clear <= 1'b 0;

timer_n #( .NBITS ( 7 ), .NTICKS ( 100 ) )
u26 (
.clock ( clock ),
.clear ( 1'b 0 ),
.load ( clear_event ),
.count ( sample_1ms & !clear_done ),
.done ( clear_done )
);

// Module asynchronous clear trigger and interval timer ( 10 ms )

wire logic_clear_done;
reg logic_clear;

always @( posedge clock, posedge clear )

if ( clear ) logic_clear <= 1'b 1;
else if ( logic_clear_done ) logic_clear <= 1'b 0;

timer_n #( .NBITS ( 4 ), .NTICKS ( 10 ) )
u27 (
.clock ( clock ),
.clear ( 1'b 0 ),
.load ( clear ),
.count ( sample_1ms & !logic_clear_done ),
.done ( logic_clear_done )
);