entity freset is
generic (TEMP_DELAY :integer);
    port (
        CLK_INP        : in STD_LOGIC;
        SENSOR_INP    : in STD_LOGIC;
        RESET_OUT    : out STD_LOGIC);
end freset;

architecture res_body of freset is
signal cnt_div_s: INTEGER range TEMP_DELAY-1 downto 0 := (TEMP_DELAY-1);-------  начальное состояние

begin
AVT_OUT_machine: process (CLK_INP)
begin
    if rising_edge(CLK_INP) then
        if cnt_div_s /= 0 and SENSOR_INP = '1' then
            cnt_div_s <= cnt_div_s-1;
            RESET_OUT <= '0';
        else
            RESET_OUT <= '1';
        end if;
    end if;
end process;
end res_body;
----------------------------------
    signal init_s : STD_LOGIC:='1';-------  начальное состояние
    signal tnit_s : STD_LOGIC:='0';
    signal RESET  : STD_LOGIC;
begin
nu: process (CLK)
begin
    if rising_edge(CLK) then
    tnit_s <= not RESET;
        if tnit_s ='1' and RESET ='1' then
            init_s <= '0';
        end if;
    end if;
end process nu;

    rest:    freset
generic map(100)
    port map (
        CLK_INP        =>  CLK,
        SENSOR_INP    =>  init_s,
                    
        RESET_OUT    =>  RESET
        );

xRST_MAIN : srlc32e
port map (
    q => rst_main_inv,
    a => "11111",
    clk => clk,
    d => '1',
    ce => '1'
);

rst_main <= (not rst_main_inv);