module FSM_Logic (
                input [...:0] CurState,
                input [...:0] DependentVar,
                output reg [...:0] NextState
                );          
          always @(*)
       case (CurState, DependentVar)
             {} : if ()  NextState = {};
             .......
             default: NextState = {};
       endcase        
endmodule




module FSM (
        input Clk,
       ...............
       output reg [...:0] CurState,
       ...............
      );

    .........
    war [...:0] NextState;
    reg [...:0] DependentVar;
    .........
                
                FSM_Logic FSM_Logic_Component (
                    .CurState(CurState),
                   .DependentVar(DependentVar)
                   .NextState(NextState))
        /* synthesis altera_implement_in_eab=1 */;
          
    always @(posedge Clk,.....)
             CurState <= NextState;
    
    ........................            

endmodule