void DMA2_Stream5_IRQHandler ( void )
{
    uart2_putcharPoll ( 'I' );//, xNoBlock );

    portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;

    if ( DMA_GetITStatus ( SPI_DMA_MASTER_Tx_DMA_Stream, DMA_IT_TCIF5 ) == SET )
    {
        uart2_putcharPoll ( 'F' );//, xNoBlock );

//         Clear DMA Stream Transfer Complete interrupt pending bit

        if ( CurrentBufSPI1 == buf1 )
        {
            CurrentBufSPI1 = buf2;
            uart2_putcharPoll ( '2' );//, xNoBlock );
        }

        if ( CurrentBufSPI1 == buf2 )
        {
            CurrentBufSPI1 = buf1;
            uart2_putcharPoll ( '1' );//, xNoBlock );
        }
        DMA_Cmd ( SPI_DMA_MASTER_Tx_DMA_Stream, DISABLE );
        DMA_ClearITPendingBit ( SPI_DMA_MASTER_Tx_DMA_Stream, DMA_IT_TCIF5 );
    }
    xSemaphoreGiveFromISR ( xSemaphore_spi1, &xHigherPriorityTaskWoken );
    xTaskResumeFromISR (&xHandleSPI1);
    uart2_putcharPoll ( 'E' );//, xNoBlock );
    portEND_SWITCHING_ISR ( xHigherPriorityTaskWoken );
}

void Task_SPI1 ( void *pvParameters )
{
    xSemaphoreTake ( xSemaphore_spi1, portMAX_DELAY );

    for (;; )
    {
        if ( CurrentBufSPI1 == buf1 )
        {
            ukladkabufTXSPI1 ( Buffer1TX_SPI1 );

            DMA_Config ( Buffer1TX_SPI1, indexTX*8 );
        }
        if ( CurrentBufSPI1 == buf2 )
                {
            ukladkabufTXSPI1 ( Buffer2TX_SPI1 );

            DMA_Config ( Buffer2TX_SPI1, indexTX*8 );
        }
            vTaskSuspend ( &xHandleSPI1 );

    }
}

[/code]void DMA_Config ( uint8_t * Memory0BaseAddr, uint16_t size )
{
    DMA_InitTypeDef        DMA_InitStructure;
    NVIC_InitTypeDef    NVIC_InitStructure;

    // Сброс настроек DMA каналов
    DMA_DeInit ( SPI_DMA_MASTER_Tx_DMA_Stream );

    RCC_AHB1PeriphClockCmd ( SPI_DMA_MASTER_DMA_CLK, ENABLE );

    DMA_DeInit(SPIx_TX_DMA_STREAM);
    /* Configure DMA Initialization Structure */
      DMA_InitStructure.DMA_BufferSize = size;
      DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
      DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
      DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
      DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
      DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
      DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
      DMA_InitStructure.DMA_PeripheralBaseAddr =(uint32_t) (&(SPIx->DR));
      DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
      DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
      DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
      DMA_InitStructure.DMA_Priority = DMA_Priority_High;
      /* Configure TX DMA */
      DMA_InitStructure.DMA_Channel = SPIx_TX_DMA_CHANNEL;
      DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
      DMA_InitStructure.DMA_Memory0BaseAddr =(uint32_t)Memory0BaseAddr;
      DMA_Init(SPIx_TX_DMA_STREAM, &DMA_InitStructure);

    // Configure the DMA interrupt priority
    NVIC_InitStructure.NVIC_IRQChannel = DMAx_Streamx_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init ( &NVIC_InitStructure );

    SPI_I2S_ITConfig ( SPIx, SPI_I2S_IT_TXE, ENABLE );

    DMA_ClearITPendingBit ( SPI_DMA_MASTER_Tx_DMA_Stream, SPI_DMA_MASTER_Tx_DMA_IT );
    DMA_ClearFlag ( SPI_DMA_MASTER_Tx_DMA_Stream, SPI_DMA_MASTER_Tx_DMA_FLAG );

    SPI_I2S_DMACmd ( SPI_DMA_MASTER, SPI_I2S_DMAReq_Tx, ENABLE );
    DMA_ITConfig ( SPI_DMA_MASTER_Tx_DMA_Stream, DMA_IT_TC, ENABLE );
    DMA_Cmd ( SPI_DMA_MASTER_Tx_DMA_Stream, ENABLE );
}

#define SPI_DMA_MASTER                    SPI1
#define SPI_DMA_MASTER_DMA                DMA2
#define SPI_DMA_MASTER_DMA_CLK            RCC_AHB1Periph_DMA2
#define SPI_DMA_MASTER_Tx_DMA_Stream    DMA2_Stream5
#define SPI_DMA_MASTER_Tx_DMA_Channel    DMA_Channel_3
#define SPI_DMA_MASTER_Tx_DMA_FLAG        DMA_FLAG_TCIF5
#define SPI_DMA_MASTER_Tx_DMA_IT        DMA_IT_TCIF5
#define DMAx_Streamx_IRQn                DMA2_Stream5_IRQn

#define SPIx_DMA                        DMA2
#define SPIx_DMA_CLK                    RCC_AHB1Periph_DMA2
#define SPIx_TX_DMA_CHANNEL             DMA_Channel_3
#define SPIx_TX_DMA_STREAM              DMA2_Stream5
#define SPIx_TX_DMA_FLAG_TCIF           DMA_FLAG_TCIF5