// app_NiosII.v

// Generated using ACDS version 16.1 196

`timescale 1 ps / 1 ps
module app_NiosII (
input wire clk_clk, // clk.clk
input wire [7:0] pio_in_external_connection_export, // pio_in_external_connection.export
output wire [7:0] pio_out_external_connection_export, // pio_out_external_connection.export
input wire reset_reset_n // reset.reset_n
);

wire [31:0] nios2_qsys_data_master_readdata; // mm_interconnect_0:nios2_qsys_data_master_readdata -> nios2_qsys:d_readdata
wire nios2_qsys_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_data_master_waitrequest -> nios2_qsys:d_waitrequest
wire nios2_qsys_data_master_debugaccess; // nios2_qsys:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_data_master_debugaccess
wire [18:0] nios2_qsys_data_master_address; // nios2_qsys:d_address -> mm_interconnect_0:nios2_qsys_data_master_address
wire [3:0] nios2_qsys_data_master_byteenable; // nios2_qsys:d_byteenable -> mm_interconnect_0:nios2_qsys_data_master_byteenable
wire nios2_qsys_data_master_read; // nios2_qsys:d_read -> mm_interconnect_0:nios2_qsys_data_master_read
wire nios2_qsys_data_master_write; // nios2_qsys:d_write -> mm_interconnect_0:nios2_qsys_data_master_write
wire [31:0] nios2_qsys_data_master_writedata; // nios2_qsys:d_writedata -> mm_interconnect_0:nios2_qsys_data_master_writedata
wire [31:0] nios2_qsys_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_instruction_master_readdata -> nios2_qsys:i_readdata
wire nios2_qsys_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_instruction_master_waitrequest -> nios2_qsys:i_waitrequest
wire [18:0] nios2_qsys_instruction_master_address; // nios2_qsys:i_address -> mm_interconnect_0:nios2_qsys_instruction_master_address
wire nios2_qsys_instruction_master_read; // nios2_qsys:i_read -> mm_interconnect_0:nios2_qsys_instruction_master_read
wire [31:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata; // nios2_qsys:jtag_debug_module_readdata -> mm_interconnect_0:nios2_qsys_jtag_debug_module_readdata
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest; // nios2_qsys:jtag_debug_module_waitrequest -> mm_interconnect_0:nios2_qsys_jtag_debug_module_waitrequest
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess; // mm_interconnect_0:nios2_qsys_jtag_debug_module_debugaccess -> nios2_qsys:jtag_debug_module_debugaccess
wire [8:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_address; // mm_interconnect_0:nios2_qsys_jtag_debug_module_address -> nios2_qsys:jtag_debug_module_address
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_read; // mm_interconnect_0:nios2_qsys_jtag_debug_module_read -> nios2_qsys:jtag_debug_module_read
wire [3:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable; // mm_interconnect_0:nios2_qsys_jtag_debug_module_byteenable -> nios2_qsys:jtag_debug_module_byteenable
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_write; // mm_interconnect_0:nios2_qsys_jtag_debug_module_write -> nios2_qsys:jtag_debug_module_write
wire [31:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata; // mm_interconnect_0:nios2_qsys_jtag_debug_module_writedata -> nios2_qsys:jtag_debug_module_writedata
wire mm_interconnect_0_onchip_memory_s1_chipselect; // mm_interconnect_0:onchip_memory_s1_chipselect -> onchip_memory:chipselect
wire [31:0] mm_interconnect_0_onchip_memory_s1_readdata; // onchip_memory:readdata -> mm_interconnect_0:onchip_memory_s1_readdata
wire [14:0] mm_interconnect_0_onchip_memory_s1_address; // mm_interconnect_0:onchip_memory_s1_address -> onchip_memory:address
wire [3:0] mm_interconnect_0_onchip_memory_s1_byteenable; // mm_interconnect_0:onchip_memory_s1_byteenable -> onchip_memory:byteenable
wire mm_interconnect_0_onchip_memory_s1_write; // mm_interconnect_0:onchip_memory_s1_write -> onchip_memory:write
wire [31:0] mm_interconnect_0_onchip_memory_s1_writedata; // mm_interconnect_0:onchip_memory_s1_writedata -> onchip_memory:writedata
wire mm_interconnect_0_onchip_memory_s1_clken; // mm_interconnect_0:onchip_memory_s1_clken -> onchip_memory:clken
wire mm_interconnect_0_pio_out_s1_chipselect; // mm_interconnect_0:pio_out_s1_chipselect -> pio_out:chipselect
wire [31:0] mm_interconnect_0_pio_out_s1_readdata; // pio_out:readdata -> mm_interconnect_0:pio_out_s1_readdata
wire [1:0] mm_interconnect_0_pio_out_s1_address; // mm_interconnect_0:pio_out_s1_address -> pio_out:address
wire mm_interconnect_0_pio_out_s1_write; // mm_interconnect_0:pio_out_s1_write -> pio_out:write_n
wire [31:0] mm_interconnect_0_pio_out_s1_writedata; // mm_interconnect_0:pio_out_s1_writedata -> pio_out:writedata
wire [31:0] mm_interconnect_0_pio_in_s1_readdata; // pio_in:readdata -> mm_interconnect_0:pio_in_s1_readdata
wire [1:0] mm_interconnect_0_pio_in_s1_address; // mm_interconnect_0:pio_in_s1_address -> pio_in:address
wire [31:0] nios2_qsys_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys:d_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_qsys_reset_n_reset_bridge_in_reset_reset, nios2_qsys:reset_n, onchip_memory:reset, pio_in:reset_n, pio_out:reset_n, rst_translator:in_reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys:reset_req, onchip_memory:reset_req, rst_translator:reset_req_in]
wire nios2_qsys_jtag_debug_module_reset_reset; // nios2_qsys:jtag_debug_module_resetrequest -> rst_controller:reset_in1

app_NiosII_nios2_qsys nios2_qsys (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_qsys_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_data_master_read), // .read
.d_readdata (nios2_qsys_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_data_master_write), // .write
.d_writedata (nios2_qsys_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (nios2_qsys_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_instruction_master_read), // .read
.i_readdata (nios2_qsys_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
.d_irq (nios2_qsys_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (nios2_qsys_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_nios2_qsys_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_nios2_qsys_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_nios2_qsys_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);

app_NiosII_onchip_memory onchip_memory (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);

app_NiosII_pio_in pio_in (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_in_s1_address), // s1.address
.readdata (mm_interconnect_0_pio_in_s1_readdata), // .readdata
.in_port (pio_in_external_connection_export) // external_connection.export
);

app_NiosII_pio_out pio_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_out_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_out_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_out_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_out_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_out_s1_readdata), // .readdata
.out_port (pio_out_external_connection_export) // external_connection.export
);

app_NiosII_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.nios2_qsys_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_reset_n_reset_bridge_in_reset.reset
.nios2_qsys_data_master_address (nios2_qsys_data_master_address), // nios2_qsys_data_master.address
.nios2_qsys_data_master_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
.nios2_qsys_data_master_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
.nios2_qsys_data_master_read (nios2_qsys_data_master_read), // .read
.nios2_qsys_data_master_readdata (nios2_qsys_data_master_readdata), // .readdata
.nios2_qsys_data_master_write (nios2_qsys_data_master_write), // .write
.nios2_qsys_data_master_writedata (nios2_qsys_data_master_writedata), // .writedata
.nios2_qsys_data_master_debugaccess (nios2_qsys_data_master_debugaccess), // .debugaccess
.nios2_qsys_instruction_master_address (nios2_qsys_instruction_master_address), // nios2_qsys_instruction_master.address
.nios2_qsys_instruction_master_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
.nios2_qsys_instruction_master_read (nios2_qsys_instruction_master_read), // .read
.nios2_qsys_instruction_master_readdata (nios2_qsys_instruction_master_readdata), // .readdata
.nios2_qsys_jtag_debug_module_address (mm_interconnect_0_nios2_qsys_jtag_debug_module_address), // nios2_qsys_jtag_debug_module.address
.nios2_qsys_jtag_debug_module_write (mm_interconnect_0_nios2_qsys_jtag_debug_module_write), // .write
.nios2_qsys_jtag_debug_module_read (mm_interconnect_0_nios2_qsys_jtag_debug_module_read), // .read
.nios2_qsys_jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata), // .readdata
.nios2_qsys_jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata), // .writedata
.nios2_qsys_jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable), // .byteenable
.nios2_qsys_jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
.nios2_qsys_jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
.onchip_memory_s1_address (mm_interconnect_0_onchip_memory_s1_address), // onchip_memory_s1.address
.onchip_memory_s1_write (mm_interconnect_0_onchip_memory_s1_write), // .write
.onchip_memory_s1_readdata (mm_interconnect_0_onchip_memory_s1_readdata), // .readdata
.onchip_memory_s1_writedata (mm_interconnect_0_onchip_memory_s1_writedata), // .writedata
.onchip_memory_s1_byteenable (mm_interconnect_0_onchip_memory_s1_byteenable), // .byteenable
.onchip_memory_s1_chipselect (mm_interconnect_0_onchip_memory_s1_chipselect), // .chipselect
.onchip_memory_s1_clken (mm_interconnect_0_onchip_memory_s1_clken), // .clken
.pio_in_s1_address (mm_interconnect_0_pio_in_s1_address), // pio_in_s1.address
.pio_in_s1_readdata (mm_interconnect_0_pio_in_s1_readdata), // .readdata
.pio_out_s1_address (mm_interconnect_0_pio_out_s1_address), // pio_out_s1.address
.pio_out_s1_write (mm_interconnect_0_pio_out_s1_write), // .write
.pio_out_s1_readdata (mm_interconnect_0_pio_out_s1_readdata), // .readdata
.pio_out_s1_writedata (mm_interconnect_0_pio_out_s1_writedata), // .writedata
.pio_out_s1_chipselect (mm_interconnect_0_pio_out_s1_chipselect) // .chipselect
);

app_NiosII_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sender_irq (nios2_qsys_d_irq_irq) // sender.irq
);

altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);

endmodule