set_time_format -unit ns -decimal_places 3

# create_clock -name clk_in -period "100 MHz" -waveform {0 5.0} ClkIn
create_clock -name clk_in -period "100 MHz" [get_ports ClkIn]

create_clock -name clk_virt -period "100 MHz"

# create_generated_clock -name clk_div ClkDiv -divide_by 2 -source ClkIn
create_generated_clock -name clk_div -divide_by 2 -source [get_ports ClkIn] \
    [get_registers ClkDiv]

set_clock_groups -exclusive -group {clk_in} -group {clk_div}

derive_clock_uncertainty

# set_input_delay -clock clk_virt -min 0.0 ClkSel
# set_input_delay -clock clk_virt -max 1.0 ClkSel

# set_input_delay -clock clk_virt -min 0.0 ResetN
# set_input_delay -clock clk_virt -max 1.0 ResetN

# set_input_delay -clock clk_virt -min 0.0 DataIn
# set_input_delay -clock clk_virt -max 1.0 DataIn

set_input_delay -clock clk_virt -min 0.0 [all_inputs]
# max -> iExt
set_input_delay -clock clk_virt -max 0.4 [all_inputs]

set_output_delay -clock clk_virt -min 0.0 ClkOut
# max -> -oExt
set_output_delay -clock clk_virt -max 0.8 ClkOut

set_output_delay -clock clk_virt -min 0.0 DataOut
set_output_delay -clock clk_virt -max 1.2 DataOut

# set_output_delay -clock clk_virt -min 0.0 [all_outputs]
# set_output_delay -clock clk_virt -max 1.0 [all_outputs]

set_min_delay -from ClkIn -to ClkOut 0.6
set_max_delay -from ClkIn -to ClkOut 8.0
set_min_delay -from ClkSel -to ClkOut 1.0
set_max_delay -from ClkSel -to ClkOut 8.0