module ram_test(q, a, d, we, clk);
output reg [7:0] q;
input [7:0] d;
input [6:0] a;
input we, clk;

reg [6:0] read_add=32,read_add_d;
reg [7:0] mem [127:0] /* synthesis syn_ramstyle="block_ram" */;

always @(posedge clk) read_add_d <= read_add;

always @(posedge clk) begin
    if(we)
        //Register RAM data and read address
        mem[read_add_d] <= d;
        read_add <= a;
    end
    
always @(posedge clk) q <= mem[read_add_d];

----------------------------------------------------------------------------------
@N: MF135 :"e:\bram_test\frontend\rtl\components\bram\sdp_ram_rtl.sv":12:0:12:5|Found RAM, 'mem[7:0]', 128 words by 8 bits
@W:"e:\bram_test\frontend\rtl\components\bram\sdp_ram_rtl.sv":12:0:12:5|Ram mem[7:0] will be mapped into logic and will consume around 1024 register resources.

----------------------------------------------------------------------------------
Total LUTs:  1904 of 2880 (66%)
Logic resources:  1904 LCs of 2880 (66%)
Number of Nets:   1939
Number of Inputs: 8464
Register bits:    1048 (1024 using enable)
EABs:             0  (0% of 10)
I/O cells:       25