Info: Changing the current directory to output directory C:/intelFPGA/16.1/active_hdl_libs ..
Info: Using Path C:/Aldec/Active-HDL-10.3-x64/BIN that was set in EDA Simulation Library Compiler Options
Info: Generating commands to compile library altera_ver ...
Info: Generating commands to compile library lpm_ver ...
Info: Generating commands to compile library sgate_ver ...
Info: Generating commands to compile library altera_mf_ver ...
Info: Generating commands to compile library altera_lnsim_ver ...
Info: Executing command file containing library compilation commands
Info: VHDL/Verilog/EDIF/SystemC Simulator build 10.3.3558.6081
Info: © 1997-2016 Aldec, Inc. All rights reserved.
Info: License Number 0
Info: VSIMSA: Configuration files: `C:\Aldec\Active-HDL-10.3-x64\vlib\library.cfg', `C:\Aldec\Active-HDL-10.3-x64\BIN\vsimsa.cfg'
Info: Welcome to VSIMSA!
Info: This message was printed from `startup.do' macro file.
Info: alib -global altera_ver "C:/intelFPGA/16.1/active_hdl_libs/verilog_libs/altera_ver"
Info: "attrib" не является внутренней или внешней
Info: командой, исполняемой программой или пакетным файлом.
Info: "attrib" не является внутренней или внешней
Info: командой, исполняемой программой или пакетным файлом.
Error: ALIB: Error: Cannot create library
Info: temp_simlib_comp.tmp(2) Script: Break at line 2.
Info: onerror { exit }

Info: "attrib" не является внутренней или внешней
Info: командой, исполняемой программой или пакетным файлом.

Info: Changing the current directory to output directory C:/Aldec/Active-HDL-10.4/Libraries/Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries ..
Info: Using Path C:/Aldec/Active-HDL-10.4/BIN that was set in EDA Simulation Library Compiler Options
Info: Generating commands to compile library altera_ver ...
Info: Generating commands to compile library lpm_ver ...
Info: Generating commands to compile library sgate_ver ...
Info: Generating commands to compile library altera_mf_ver ...
Info: Generating commands to compile library altera_lnsim_ver ...
Info: Executing command file containing library compilation commands
Info: VHDL/Verilog/EDIF/SystemC Simulator build 10.4.183.6396
Info: © 1997-2016 Aldec, Inc. All rights reserved.
Info: License Number 0
Info: VSIMSA: Configuration files: `C:\Aldec\Active-HDL-10.4\vlib\library.cfg', `C:\Aldec\Active-HDL-10.4\BIN\vsimsa.cfg'
Info: Welcome to VSIMSA!
Info: This message was printed from `startup.do' macro file.
Info: alib -global altera_ver "C:/Aldec/Active-HDL-10.4/Libraries/Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries/verilog_libs/altera_ver"
Info: ALIB: Library `altera_ver' attached.
Info: altera_ver = C:\Aldec\Active-HDL-10.4\Libraries\Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries\verilog_libs\altera_ver\altera_ver.lib
Info: alog -dbg -work altera_ver -v2k "d:/altera/13.0sp1/quartus/eda/sim_lib/altera_primitives.v"
Info: Pass 1. Scanning modules hierarchy.
Info: Pass 2. Processing instantiations.
Info: Pass 3. Processing behavioral statements.
Info: ELB/DAG code generating.
Info: Unit top modules: global carry cascade carry_sum exp soft opndrn row_global TRI lut_input lut_output latch dlatch dff dffe dffea dffeas tff tffe jkff jkffe srff srffe clklock alt_inbuf alt_outbuf alt_outbuf_tri alt_iobuf alt_inbuf_diff alt_outbuf_diff alt_outbuf_tri_diff alt_iobuf_diff alt_bidir_diff alt_bidir_buf.
Info: $root top modules: global carry cascade carry_sum exp soft opndrn row_global TRI lut_input lut_output latch dlatch dff dffe dffea dffeas tff tffe jkff jkffe srff srffe clklock alt_inbuf alt_outbuf alt_outbuf_tri alt_iobuf alt_inbuf_diff alt_outbuf_diff alt_outbuf_tri_diff alt_iobuf_diff alt_bidir_diff alt_bidir_buf.
Info: Compile success 0 Errors 0 Warnings Analysis time: 4[s].
Info: done
Info: alib -global lpm_ver "C:/Aldec/Active-HDL-10.4/Libraries/Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries/verilog_libs/lpm_ver"
Info: ALIB: Library `lpm_ver' attached.
Info: lpm_ver = C:\Aldec\Active-HDL-10.4\Libraries\Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries\verilog_libs\lpm_ver\lpm_ver.lib
Info: alog -dbg -work lpm_ver -v2k "d:/altera/13.0sp1/quartus/eda/sim_lib/220model.v"
Info: Pass 1. Scanning modules hierarchy.
Info: Pass 2. Processing instantiations.
Info: Pass 3. Processing behavioral statements.
Info: ELB/DAG code generating.
Info: Unit top modules: lpm_constant lpm_inv lpm_and lpm_or lpm_xor lpm_bustri lpm_mux lpm_decode lpm_clshift lpm_add_sub lpm_compare lpm_mult lpm_divide lpm_abs lpm_counter lpm_latch lpm_ff lpm_shiftreg lpm_ram_dq lpm_ram_dp lpm_ram_io lpm_rom lpm_fifo lpm_fifo_dc lpm_inpad lpm_outpad lpm_bipad.
Info: $root top modules: lpm_constant lpm_inv lpm_and lpm_or lpm_xor lpm_bustri lpm_mux lpm_decode lpm_clshift lpm_add_sub lpm_compare lpm_mult lpm_divide lpm_abs lpm_counter lpm_latch lpm_ff lpm_shiftreg lpm_ram_dq lpm_ram_dp lpm_ram_io lpm_rom lpm_fifo lpm_fifo_dc lpm_inpad lpm_outpad lpm_bipad.
Info: Compile success 0 Errors 0 Warnings Analysis time: 2[s].
Info: done
Info: alib -global sgate_ver "C:/Aldec/Active-HDL-10.4/Libraries/Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries/verilog_libs/sgate_ver"
Info: ALIB: Library `sgate_ver' attached.
Info: sgate_ver = C:\Aldec\Active-HDL-10.4\Libraries\Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries\verilog_libs\sgate_ver\sgate_ver.lib
Info: alog -dbg -work sgate_ver -v2k "d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v"
Info: Pass 1. Scanning modules hierarchy.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v : (83, 19): Undefined module: lpm_add_sub was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v : (327, 19): Undefined module: lpm_mult was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v : (419, 15): Undefined module: lpm_divide was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v : (754, 19): Undefined module: lpm_clshift was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v : (1060, 19): Undefined module: lpm_decode was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/sgate.v : (1122, 19): Undefined module: lpm_mux was used. Port connection rules will not be checked at such instantiations.
Info: Pass 2. Processing instantiations.
Info: Pass 3. Processing behavioral statements.
Info: ELB/DAG code generating.
Info: Unit top modules: oper_add oper_addsub mux21 io_buf_tri io_buf_opdrn oper_mult tri_bus oper_div oper_mod oper_left_shift oper_right_shift oper_rotate_left oper_rotate_right oper_less_than oper_mux oper_selector oper_decoder oper_bus_mux oper_latch.
Info: $root top modules: oper_add oper_addsub mux21 io_buf_tri io_buf_opdrn oper_mult tri_bus oper_div oper_mod oper_left_shift oper_right_shift oper_rotate_left oper_rotate_right oper_less_than oper_mux oper_selector oper_decoder oper_bus_mux oper_latch.
Info: Compile success 0 Errors 6 Warnings Analysis time: 0[s].
Info: done
Info: alib -global altera_mf_ver "C:/Aldec/Active-HDL-10.4/Libraries/Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries/verilog_libs/altera_mf_ver"
Info: ALIB: Library `altera_mf_ver' attached.
Info: altera_mf_ver = C:\Aldec\Active-HDL-10.4\Libraries\Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries\verilog_libs\altera_mf_ver\altera_mf_ver.lib
Info: alog -dbg -work altera_mf_ver -v2k "d:/altera/13.0sp1/quartus/eda/sim_lib/altera_mf.v"
Info: Pass 1. Scanning modules hierarchy.
Info: Pass 2. Processing instantiations.
Info: Pass 3. Processing behavioral statements.
Info: ELB/DAG code generating.
Info: Unit top modules: lcell altpll altlvds_rx altlvds_tx dcfifo altaccumulate altmult_accum altmult_add altfp_mult altsqrt altclklock altddio_bidir altdpram alt3pram parallel_add scfifo altshift_taps a_graycounter altsquare altera_std_synchronizer_bundle alt_cal alt_cal_mm alt_cal_c3gxb alt_cal_sv alt_cal_av alt_aeq_s4 alt_eyemon alt_dfe sld_virtual_jtag sld_signaltap altstratixii_oct altparallel_flash_loader altserial_flash_loader sld_virtual_jtag_basic altsource_probe.
Info: $root top modules: lcell altpll altlvds_rx altlvds_tx dcfifo altaccumulate altmult_accum altmult_add altfp_mult altsqrt altclklock altddio_bidir altdpram alt3pram parallel_add scfifo altshift_taps a_graycounter altsquare altera_std_synchronizer_bundle alt_cal alt_cal_mm alt_cal_c3gxb alt_cal_sv alt_cal_av alt_aeq_s4 alt_eyemon alt_dfe sld_virtual_jtag sld_signaltap altstratixii_oct altparallel_flash_loader altserial_flash_loader sld_virtual_jtag_basic altsource_probe.
Info: Compile success 0 Errors 0 Warnings Analysis time: 10[s].
Info: done
Info: alib -global altera_lnsim_ver "C:/Aldec/Active-HDL-10.4/Libraries/Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries/verilog_libs/altera_lnsim_ver"
Info: ALIB: Library `altera_lnsim_ver' attached.
Info: altera_lnsim_ver = C:\Aldec\Active-HDL-10.4\Libraries\Active-HDL_10.4.183.6396_x32_for_Altera_Quartus_II_13.0.1.232_Libraries\verilog_libs\altera_lnsim_ver\altera_lnsim_ver.lib
Info: alog -dbg -work altera_lnsim_ver -sv2k5 "d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv"
Info: Pass 1. Scanning modules hierarchy.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3610, 15): Undefined module: twentynm_iopll_ip was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3739, 25): Undefined module: alt_inbuf was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3749, 26): Undefined module: alt_outbuf was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3761, 26): Undefined module: alt_iobuf was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3952, 41): Undefined module: stratixv_lcell_comb was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3965, 41): Undefined module: arriav_lcell_comb was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3978, 41): Undefined module: arriavgz_lcell_comb was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3991, 41): Undefined module: cyclonev_lcell_comb was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (5867, 7): Undefined module: stratixv_ffpll_reconfig was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (7741, 7): Undefined module: arriav_ffpll_reconfig was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (9614, 7): Undefined module: arriavgz_ffpll_reconfig was used. Port connection rules will not be checked at such instantiations.
Warning: Warning: VCP2515 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (10839, 7): Undefined module: cyclonev_ffpll_reconfig was used. Port connection rules will not be checked at such instantiations.
Info: Pass 2. Processing instantiations.
Warning: Warning: VCP2597 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (2007, 1): Some unconnected ports remain at instance: gpll. Module generic_pll has unconnected port(s) : writerefclkdata, writeoutclkdata, writephaseshiftdata, writedutycycledata, readrefclkdata, readoutclkdata, readphaseshiftdata, readdutycycledata.
Warning: Warning: VCP2597 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (2082, 1): Some unconnected ports remain at instance: dprio_init_inst. Module dprio_init has unconnected port(s) : dprio_init_done.
Warning: Warning: VCP2597 d:/altera/13.0sp1/quartus/eda/sim_lib/altera_lnsim.sv : (3656, 1): Some unconnected ports remain at instance: gpll. Module generic_pll has unconnected port(s) : writerefclkdata, writeoutclkdata, writephaseshiftdata, writedutycycledata, readrefclkdata, readoutclkdata, readphaseshiftdata, readdutycycledata.
Info: Pass 3. Processing behavioral statements.
Info: ELB/DAG code generating.
Info: Unit top modules: altera_pll generic_cdr generic_m20k generic_m10k common_porta_latches generic_28nm_hp_mlab_cell_impl generic_28nm_lc_mlab_cell_impl generic_mux generic_device_pll altera_mult_add altera_pll_reconfig_tasks.
Info: $root top modules: altera_pll generic_cdr generic_m20k generic_m10k common_porta_latches generic_28nm_hp_mlab_cell_impl generic_28nm_lc_mlab_cell_impl generic_mux generic_device_pll altera_mult_add altera_pll_reconfig_tasks.
Info: Compile success 0 Errors 15 Warnings Analysis time: 6[s].
Info: done