CRC->CR = CRC_CR_RESET;                               // сбросим регистр данных CRC Engine
  for(i = 0; i < FRAME_SIZE - 1; i++)                         // цикл по всем словам данных, кроме последнего
    CRC->DR = TxData[i];                                            // вычисляем CRC
    TxData[i] = CRC->DR;                                            // и заносим в последнее слово данных
  
  spiStartExchange(&SPID2, 12, TxData, RxData);

    Timer->ARR = DELAY1_TICKS;      // cache
    Timer->EGR = TIM_EGR_UG;        // write cache to ARR
    Timer->ARR = DELAY2_TICKS;      // cache

    Timer->ARR = DELAY1_TICKS;      // cache
    Timer->EGR = TIM_EGR_UG;        // write cache to ARR
    __DSB();
    Timer->ARR = DELAY2_TICKS;      // cache

    Timer->CR1 = 0
        | 0 * (TIM_CR1_CKD & -TIM_CR1_CKD)      // Dead-time clock, 0 = /1, 1 = /2, 2 = /4
        | 1 * TIM_CR1_ARPE                      // ARR buffering, 0 = not buffered, 1 = buffered
        | 0 * (TIM_CR1_CMS & -TIM_CR1_CMS)      // 0 = unidirectional, 1 = up/down, OC flags set when counting up
                                                // 2 = up/down, OC flags set when counting down, 3 = up/down, OC flags set when counting up or down
        | 0 * TIM_CR1_DIR                       // 0 = up, 1 = down
        | 0 * TIM_CR1_OPM                       // 1 = stop at update event
        | 1 * TIM_CR1_URS                       // Update request source, 0 = any, 1 = only counter wrap
        | 0 * TIM_CR1_UDIS                      // Update event generation disable
        | 0 * TIM_CR1_CEN                       // Counter enable
      ;

    .......
    
    Timer->ARR = DELAY1;        // cache
    __DSB();
    Timer->EGR = TIM_EGR_UG;    // write cache to ARR
    __DSB();
    Timer->ARR = DELAY2;        // cache
    
    Timer->CR1 = 0
        | 0 * (TIM_CR1_CKD & -TIM_CR1_CKD)      // Dead-time clock, 0 = /1, 1 = /2, 2 = /4
        | 1 * TIM_CR1_ARPE                      // ARR buffering, 0 = not buffered, 1 = buffered
        | 0 * (TIM_CR1_CMS & -TIM_CR1_CMS)      // 0 = unidirectional, 1 = up/down, OC flags set when counting up
                                                // 2 = up/down, OC flags set when counting down, 3 = up/down, OC flags set when counting up or down
        | 0 * TIM_CR1_DIR                       // 0 = up, 1 = down
        | 0 * TIM_CR1_OPM                       // 1 = stop at update event
        | 1 * TIM_CR1_URS                       // Update request source, 0 = any, 1 = only counter wrap
        | 0 * TIM_CR1_UDIS                      // Update event generation disable
        | 1 * TIM_CR1_CEN                       // Counter enable
      ;