void TIM4_IRQHandler(void)
{
TIM4->SR &= ~TIM_SR_UIF;
}

void cnt(void)
{
/* TIM1 init */
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* TIM1 enabled */
TIM1->PSC = 7200 - 1; /* new clock 10kHz */
TIM1->SMCR |= (TIM_SMCR_TS_0 | TIM_SMCR_TS_1); /* internal trigger_3 (ITR3) from TIM4 */
TIM1->SMCR |= (TIM_SMCR_SMS_0 | TIM_SMCR_SMS_2); /* while trigger input (TRGI) is high, counter is on */

/* TIM4 init */
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
TIM4->PSC = 7200 - 1; /* new clock 10kHz */
TIM4->ARR = 10000 - 1; /* period 1sec */
TIM4->CR1 |= TIM_CR1_DIR; /* counter used as downcounter */
TIM4->CR1 |= TIM_CR1_OPM; /* counter stops counting at the next update event (clearing the bit CEN) */
TIM4->CR2 |= TIM_CR2_MMS_0; /* COUNTER_ENABLE signal to TIM1, used as trigger output (TRGO) */
TIM4->DIER |= TIM_DIER_UIE; /* interrupt enable */

/* start counter */
NVIC_EnableIRQ(TIM4_IRQn);
TIM1->CR1 |= TIM_CR1_CEN;
TIM4->CR1 |= TIM_CR1_CEN;
}