library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DFF4 is
     port(
         D0,D1,D2,D3 : in STD_LOGIC;
         CLK : in STD_LOGIC;
         RS0,RS1,RS2,RS3 : in STD_LOGIC;
         Q0,Q1,Q2,Q3 : out STD_LOGIC := '0'
           );
end DFF4;

architecture RTL of DFF4 is
begin
    
process( CLK,RS0,RS1,RS2,RS3 )
   begin  
             
     if ( RS0='1') then    Q0 <= '0';
     elsif ( rising_edge (CLK)) then Q0 <= D0;
     end if;    
    
     if ( RS1='1') then    Q1 <= '0';
     elsif ( rising_edge (CLK)) then Q1 <= D1;
     end if;    
      
     if ( RS2='1') then    Q2 <= '0';
     elsif ( rising_edge (CLK)) then Q2 <= D2;
     end if;    
    
     if ( RS3='1') then    Q3 <= '0';
     elsif ( rising_edge (CLK) ) then Q3 <= D3;
     end if;    
    end process;    
end architecture;