** Error: (vsim-3601) Iteration limit reached at time 0 ns.

vsim -t 1ns tb

`timescale 1ps / 1ps

`include "altera_mf.v"
`include "main.v"
`include "pll.v"

module tb;
    reg clk;
    wire clk_108MHz;
    
    main main_tb(
        .clk(clk),
        .clk_108MHz(clk_108MHz));
    
    always
        #5 clk = !clk;

    initial
    begin
        clk = 0;
        #10000;    
        $stop;
    end
    
endmodule

transcript on
vlib work
vlog -sv tb.v
vsim -t 1ps tb
add wave /*
quietly radix unsigned
configure wave -timelineunits ns
run -all
wave zoom full

module generator
(
    input    clk,
    input     ena,
    output reg out
);
    wire     pulse;
    reg     [15:0]    cnt_val = 16'd0;
    reg     [15:0]    cnt_comp_val = 16'hFFFF;
    reg        [1:0]    state = 2'b00;
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

    reg     [15:0]    comp_val[3:0];
    initial
    begin
        comp_val[0] = 16'd4;
        comp_val[1] = 16'd5;
        comp_val[2] = 16'd6;
        comp_val[3] = 16'd7;
    end

    //----------------------------------------
    always @ (state) begin
        case (state)
            S0:
            begin
                cnt_comp_val = comp_val[0];
                out = 1;
            end
            S1:
            begin
                cnt_comp_val = comp_val[1];
                out = 0;
            end
            S2:
            begin
                cnt_comp_val = comp_val[2];
                out = 1;
            end
            S3:
            begin
                cnt_comp_val = comp_val[3];
                out = 0;
            end
            default:
            begin
                cnt_comp_val = 16'hFFFF;
                out = 0;
            end            
        endcase
    end

    //----------------------------------------    
    always @ (posedge clk)
    begin
        if (!ena)
            state <= S0;
        else
            case (state)
                S0:    state <= pulse? S1:S0;
                S1:    state <= pulse? S2:S1;
                S2:    state <= pulse? S3:S2;
                S3:    state <= pulse? S0:S3;
                default: state <= S0;
            endcase
    end

    //----------------------------------------
    always @(posedge clk)
    begin
        if(ena)
            if(cnt_val==cnt_comp_val)
                cnt_val = 4'b1;
            else
                cnt_val = cnt_val + 1'd1;
        else
            cnt_val = 4'd1;
    end    
    assign pulse = (cnt_val==cnt_comp_val);
    //----------------------------------------        
endmodule

`timescale 1ns / 1ns
`include "generator.v"

module tb;
    reg clk;
    reg ena;
    wire out;
    
    generator     generator1(.clk(clk), .ena(ena), .out(out));

    always #1 clk = ~clk;
    initial
    begin
        clk = 0;
        ena = 0;
        #100;
        ena = 1;
        #1000;
        $stop;
    end
    
endmodule

#transcript on
vlib work
vlog -sv tb.v
vsim -t 1ns tb
add wave /tb/*
add wave /tb/generator1/*

#quietly radix unsigned
configure wave -timelineunits ns
run -all
wave zoom full