module generator
(
    input    clk,
    input     ena,
    output reg out
);
    wire     pulse;
    reg     [15:0]    cnt_val;
    reg     [15:0]    cnt_comp_val;
    reg     [2:0]    state;
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

    reg     [15:0]    comp_val[3:0];
    initial
    begin
        comp_val[0] = 16'd4;
        comp_val[1] = 16'd5;
        comp_val[2] = 16'd6;
        comp_val[3] = 16'd7;
    end

    //----------------------------------------    
    always @ (posedge clk)
    begin
        if (ena)
        begin
            case (state)
                S0:    
                begin
                    cnt_comp_val <= comp_val[0];
                    state <= pulse? S1:S0;
                    out <= 1;
                end
                S1:    
                begin
                    cnt_comp_val <= comp_val[1];
                    state <= pulse? S2:S1;
                    out <= 0;
                end
                S2:    
                begin    
                    cnt_comp_val <= comp_val[2];
                    state <= pulse? S3:S2;
                    out <= 1;
                end
                S3:    
                begin    
                    cnt_comp_val <= comp_val[3];
                    state <= pulse? S0:S3;
                    out <= 0;
                end
                default:
                begin
                    cnt_comp_val <= comp_val[0];
                    state <= S0;
                    out <= 0;
                end
            endcase
        end
        else
        begin
            cnt_comp_val <= comp_val[0];
            state <= S0;
            out <= 0;
        end
    end

    //----------------------------------------
    always @(posedge clk)
    begin
        if(ena)
            if(cnt_val==cnt_comp_val)
                cnt_val = 4'b1;
            else
                cnt_val = cnt_val + 1'd1;
        else
            cnt_val = 4'd1;
    end    
    assign pulse = (cnt_val==cnt_comp_val);
    //----------------------------------------        
endmodule