library ieee;
use ieee.std_logic_1164.all;

entity myI2C_proc_tb is
end myI2C_proc_tb;

architecture behavioral of myI2C_proc_tb is

constant clk_period : time := 44 ns;
signal clk: std_logic := '0'; --тактовая частота модуля I2C_proc
signal Reset: std_logic := '0';
signal SCL: std_logic := '1';
signal SDA: std_logic := '1';
constant SCL_period: time := 4.35 us; --период SCLK
constant tri: time := SCL_period / 3.0; --треть периода SCK, время, за которое ничего не происходит
signal MyByte: std_logic_vector(7 downto 0);

--Объявления процедур
procedure i2c_start (signal mySCL: out std_logic; signal mySDA: out std_logic) is
begin
mySDA <= '1';
mySCL <= '1';
wait for tri;
mySDA <= '0';
wait for tri;
mySCL <= '0';
wait for tri;
end procedure i2c_start;

procedure i2c_stop (signal mySCL: out std_logic; signal mySDA: out std_logic) is
begin
mySDA <= '0';
mySCL <= '0';
wait for tri;
mySCL <= '1';
wait for tri;
mySDA <= '1';
wait for tri;
end procedure i2c_stop;

procedure i2c_writebyte (signal ySCL: out std_logic; signal ySDA: out std_logic;
signal ByteValue: in std_logic_vector(7 downto 0)) is
variable i: natural;
begin
--Передача байта:
i := 8;
-- wait for 1 ns;
while i > 0
loop
ySDA <= ByteValue(i - 1);
wait for tri;
ySCL <= '1';
wait for tri;
ySCL <= '0';
wait for tri;
i := i - 1;
end loop;
--Ожидание подтверждения:
ySDA <= 'Z';
wait for tri;
ySCL <= '1';
wait for tri;
ySCL <= '0';
wait for tri;
end procedure i2c_writebyte;

begin

--Тактовая частота:
clk <= not clk after (clk_period / 2.0 );

--Собственно моделирование
model_l:
process

begin
--Сброс схемы:
wait for clk_period * 2;
Reset <= '0';
--Посылка:
i2c_start(SCL, SDA);
MyByte(7 downto 1) <= B"0100001";
MyByte(0) <= '0';
i2c_writebyte(ySCL => SCL, ySDA => SDA, ByteValue => MyByte); --адресный байт
MyByte <= X"AA";
i2c_writebyte(SCL, SDA, MyByte);
MyByte <= X"AA";
i2c_writebyte(SCL, SDA, MyByte);
MyByte <= X"55";
i2c_writebyte(SCL, SDA, MyByte);
i2c_stop(SCL, SDA);

wait;
end process model_l;
end behavioral;