bool ReadByteI2C(BYTE addr, BYTE* data)
{
//set device adr
AT91C_BASE_TWI->TWI_MMR = (addr << 16)| AT91C_TWI_MREAD;    
//start
TWI_START();//macros
//write data
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_RXRDY));            
*data = AT91C_BASE_TWI->TWI_RHR;
//stop
TWI_STOP();//macros    
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXCOMP));
return true;
}

bool WriteByteI2C(BYTE addr, BYTE data)
{
//set device adr
AT91C_BASE_TWI->TWI_MMR = (addr << 16);
AT91C_BASE_TWI->TWI_THR = data;
//start
TWI_START();//macros
//write data
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXRDY));            
//stop
TWI_STOP();//macros
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXCOMP));
return true;
}

SIGNAL(SIG_2WIRE_SERIAL)
{
//TEST0_ON();
TWCB.sta = TWSR & 0xf8;
switch(TWCB.sta)
    {
//SLAVE    RECEIVE

        case TWS_SLAW_ACK:
            //SLAVE device has been addressed by SLAW
            {
            TWCR = TW_EXE_ACK;    //generate ACK
            break;
            }
        case TWS_DATAR_ACK_SLAW:
            //SLAVE has been got a byte, ACK will generated
            {
            //TEST1_ON();
            data = TWDR;
            TWCR = TW_EXE_ACK;    //switch to adressed mode
            break;
            }
        case TWS_STOP:
            //stop condition has been detected
            {
            TWCR = TW_EXE_ACK;    //& generate ACK
            break;
            }
//SLAVE TRANSMIT
        case TWS_SLAR_ACK:
            //SLAVE device has been addressed by SLAR
            {
            TWDR = 0x55;
            TWCR = TW_EXE_NACK;    //generate NACK
            break;
            }
        case TWS_DATAW_ACK:
            //SLAVE has been transmit a byte and got ACK
            //SLAVE transmit next byte
            {
            break;
            }
        case TWS_DATAW_NACK:
            //SLAVE has been transmit a byte and got NACK
            //end of transmision
            {
            TWCR = TW_EXE_ACK;    //switch to adressed mode
            break;
            }
        }
    }//switch
}
//
//
//
//TW commands
#define    TW_EXE_STA    (1<<TWINT)|(1<<TWIE)|(1<<TWEN)|(1<<TWSTA)    //make start condition
#define    TW_EXE_STO    (1<<TWINT)|(1<<TWIE)|(1<<TWEN)|(1<<TWSTO)    //make stop condition
#define    TW_EXE_ACK    (1<<TWINT)|(1<<TWIE)|(1<<TWEN)|(1<<TWEA)    //transmit byte and wait ACK
#define    TW_EXE_NACK    (1<<TWINT)|(1<<TWIE)|(1<<TWEN)                //transmit byte and wait NACK




//SLAVE RECEIVER
#define TWS_SLAW_ACK        0x60
#define TWS_ARB_LOST_SLAW    0x68
#define TWS_GEN_CALL        0x70
#define TWS_ARB_LOST_GC        0x78
#define TWS_DATAR_ACK_SLAW    0x80
#define TWS_DATAR_NACK_SLAW    0x88
#define TWS_DATAR_ACK_GC    0x90
#define TWS_DATAR_NACK_GC    0x98
#define TWS_STOP            0xa0

//SLAVE TRANSMITTER
#define TWS_SLAR_ACK        0xa8
#define TWS_ARB_LOST_SLAR    0xb0
#define TWS_DATAW_ACK        0xb8
#define TWS_DATAW_NACK        0xc0
#define TWS_DATA_LAST        0xc8

//--------------------------------------------------------------------------
void InitI2C(void)
{
//device on
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,(1 << AT91C_ID_TWI));
//enable device
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_SWRST;
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSEN;
//clock config
AT91C_BASE_TWI->TWI_CWGR =    ((0x22 << 0)    |    //clk_lo
                            (0x22 << 8)    |    //clk_hi
                            (3 << 16));
}
//--------------------------------------------------------------------------

//* Set control register and send start
*AT91C_TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN | AT91C_TWI_STOP;

//* Wait complete by TXCOMP or TXRDY
Status = *AT91C_TWI_SR;
while (!(status & AT91C_TWI_TXCOMP)){
Status = *AT91C_TWI_SR; }

//* Get data
Value = *AT91C_TWI_RHR;

//* Set control register
*AT91C_TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN | AT91C_TWI_STOP;

//* Set Data register for start transmission
*AT91C_TWI_THR = 0XAA;

//* Wait end transmission
Status = *AT91C_TWI_SR;
while (!(status & AT91C_TWI_TXCOMP)){
Status = *AT91C_TWI_SR; }

bool ReadByteI2C(BYTE addr, BYTE* data)
{
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*data = AT91C_BASE_TWI->TWI_RHR;
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//set device & internal adr
AT91C_BASE_TWI->TWI_MMR = (addr << 16)| AT91C_TWI_MREAD;    //start
TWI_START();
//write data
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_RXRDY));            
*data = AT91C_BASE_TWI->TWI_RHR;
//stop
TWI_STOP();    
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXCOMP));
//*data = AT91C_BASE_TWI->TWI_RHR;
return true;
}

#define TWI_START()        AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START;
#define TWI_STOP()        AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;

int  main(void)
{

cli();
adr = eeprom_read_byte(ADR);
DDRD = 0xff;
PORTD = port;
TWS_Init(0x10);
//enable interrupts
sei();

//--------------------------------------------------------------------------
//main loop
for(;;)
    {
    //PORTD++;
    }
return 0;
}//main

__inline__ void TWS_Init(BYTE addr)
{
TWAR = (addr << 1);
TWCR = (1 << TWEN) | (1 << TWIE) |(1 << TWEA);

//------------------------------------------------------------------------
#ifdef _MEGA8_
SIGNAL(SIG_OUTPUT_COMPARE2)
#endif
#ifdef _MEGA88_
SIGNAL(SIG_OUTPUT_COMPARE2A)
#endif
{  
//sinchronous timer operation, 100uS
    system_timer.timer_100us++;
    if(hTimer_100us) hTimer_100us();    
    if(system_timer.timer_100us >= 10)    //100uS * 10 = 1uS
        {
        system_timer.timer_1ms++;
        system_timer.timer_100us = 0;
        if(hTimer_1ms) hTimer_1ms();
        }
    if(system_timer.timer_1ms >= 1000)    //1mS * 1000 = 1s
        {
        system_timer.timer_1s++;
        system_timer.timer_1ms = 0;
        if(hTimer_1s) hTimer_1s();
        }
        
}
//------------------------------------------------------------------------
void InitSysTimer2(void)
{
TCNT2 = 0;
#ifdef _MEGA8_
//OCR2 = 138;
//OCR2 = 8;
OCR2 = 14;
TCCR2 = 0;
TCCR2 = (1 << WGM21)|(1 << CS21);//CTC mode
//TCCR2 = (1 << WGM21)|(1 << CS20);//CTC mode
//TCCR2 = (1 << WGM21)|(1 << CS22)|(1 << CS20);//CTC mode
TIMSK |= (1 << OCIE2);
#endif
#ifdef _MEGA88_
OCR2A = 138;
TCCR2A = 0;
TCCR2A = (1<< WGM21);//;//CTC mode
TCCR2B = 0;
//TCCR2B = (1 << CS21);//clk/8    
TCCR2B = (1 << CS22)|(1 << CS20);//clk/128    
TIMSK2 |= (1<<OCIE2A);
#endif
}
//------------------------------------------------------------------------

void AT24WriteMem(DWORD addr, BYTE* src, DWORD len)
{
while(len)
    {
    AT24WriteByte(addr,*src);
    addr++;
    src++;
    len--;
    }
}

bool AT24WriteByte(DWORD addr, BYTE data)
{
//set device & internal adr
AT91C_BASE_TWI->TWI_MMR = (AT91C_TWI_IADRSZ_2_BYTE|(0x50 << 16));
AT91C_BASE_TWI->TWI_IADR = addr;
AT91C_BASE_TWI->TWI_THR = data;
//start
TWI_START();
//write data
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXRDY));            
//stop
TWI_STOP();    
while(!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXCOMP));
return true;
}

void AT24ReadMem(DWORD addr, BYTE* src, DWORD len)
{
//DWORD AT24_Read(BYTE* data, BYTE dadr, DWORD address,  DWORD size)
unsigned int status;
// Set the TWI Master Mode Register
AT91C_BASE_TWI->TWI_MMR = (0x50 << 16)| AT91C_TWI_IADRSZ_2_BYTE | AT91C_TWI_MREAD;    
// Set TWI Internal Address Register
AT91C_BASE_TWI->TWI_IADR = addr;
// Start transfer
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START;
status = AT91C_BASE_TWI->TWI_SR;
while (len-- >1)
    {
    // Wait RHR Holding register is full
    while (!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_RXRDY));
    // Read byte
    *(src++) = AT91C_BASE_TWI->TWI_RHR;
    }
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP;
status = AT91C_BASE_TWI->TWI_SR;
// Wait transfer is finished
while (!(AT91C_BASE_TWI->TWI_SR & AT91C_TWI_TXCOMP));
// Read last byte
*src = AT91C_BASE_TWI->TWI_RHR;
}