`timescale 1 ns / 1 ps

module CLOCK_DIV ( CLK80MHz ,SELECT_CLK ,CLK_OUT,CLK_OUT_INV );

output CLK_OUT;
reg CLK_OUT;
output CLK_OUT_INV;
reg CLK_OUT_INV;
input CLK80MHz;
input [3:0] SELECT_CLK;

reg [8:0] DIVIDER;
reg CLK_OUT_INT;
wire CLK_OUT_INV_INT;

always@(posedge CLK80MHz)
    DIVIDER<=DIVIDER+1;
    
always@(SELECT_CLK,DIVIDER)
    casex(SELECT_CLK)
        4'b0001:CLK_OUT_INT<=DIVIDER[8]; //freq=156250 Hz;
        4'b0010:CLK_OUT_INT<=DIVIDER[7]; //freq=312500 Hz;
        4'b0100:CLK_OUT_INT<=DIVIDER[6]; //freq=625000 Hz;
        4'b1000:CLK_OUT_INT<=DIVIDER[5]; //freq=1250000 Hz;
        default: CLK_OUT_INT<=DIVIDER[5];
    endcase      
    
assign CLK_OUT_INV_INT=!CLK_OUT_INT;
    
always@(posedge CLK80MHz)
    begin
    CLK_OUT_INV<=CLK_OUT_INV_INT;
    CLK_OUT<=CLK_OUT_INT;      
    end
    
endmodule