void InitSPI (void)
{

        XSpi_mSetControlReg(XPAR_OPB_SPI_0_BASEADDR, (XSP_CR_ENABLE_MASK | XSP_CR_MASTER_MODE_MASK | XSP_MANUAL_SSELECT_OPTION));
}

void SET_SLAVE_SSB_LOW (void)
{
     XGpio_mWriteReg (XPAR_LEDS_8BIT_BASEADDR,0x00,(SPI_SLAVE_NORMAL_MODE | SPI_SSB_LOW));
     //affects SPISSR (SPI Slave Relect Register on Default =1;
    // xil_printf("SPI_SSB set LOW \r\n");
}    

void SET_SLAVE_SSB_HIGH (void)
{
      XGpio_mWriteReg (XPAR_LEDS_8BIT_BASEADDR,0x00,(SPI_SLAVE_NORMAL_MODE | SPI_SSB_HIGH));  
     // xil_printf("SPI_SSB set HIGH \r\n");
}

void SPI_WRITE_DATA (char INTERNAL_ADRESS, char SEND_DATA)
{

   SET_SLAVE_SSB_LOW();
    XSpi_mSendByte(XPAR_OPB_SPI_0_BASEADDR,((INTERNAL_ADRESS<<1)|WRITE));
        while ( XSpi_mGetStatusReg(XPAR_OPB_SPI_0_BASEADDR)&XSP_SR_RX_EMPTY_MASK )
        { }
       XSpi_mRecvByte(XPAR_OPB_SPI_0_BASEADDR);
      //      }
    XSpi_mSendByte(XPAR_OPB_SPI_0_BASEADDR, SEND_DATA);
        while ( XSpi_mGetStatusReg(XPAR_OPB_SPI_0_BASEADDR)&XSP_SR_RX_EMPTY_MASK )
        { }
    XSpi_mRecvByte(XPAR_OPB_SPI_0_BASEADDR);
     //       }    
   SET_SLAVE_SSB_HIGH();          
}

void IIC_init(XIic MY_Iic)
{
Xuint32 Iic_status;
XIic_Initialize  (&MY_Iic, XPAR_OPB_IIC_0_DEVICE_ID);
XIic_SetOptions (&MY_Iic,XIIC_CR_ENABLE_DEVICE_MASK);
XIic_Start(&MY_Iic);
Iic_status= XIic_SelfTest(&MY_Iic);
    if(Iic_status== XST_SUCCESS){
        xil_printf("IIC selftest succesful \r\n");
      }
      else{      
       xil_printf("IIC some errors detected \r\n");
        }

}

void main(void)
{      
       while(1)
          {
                  XIic_MasterSend  (&MY_Iic,0x55,1);  
          }
            
}

#define SLAVE_STARTING_ADDRESS        0x00    // set the starting slave address    
XSpi_Initialize(&MY_Spi, SLAVE_STARTING_ADDRESS);

xspi.h

[b]#define XSP_MASTER_OPTION           0x1
#define XSP_CLK_ACTIVE_LOW_OPTION   0x2[/b]
#define XSP_CLK_PHASE_1_OPTION      0x4
#define XSP_LOOPBACK_OPTION         0x8
#define XSP_MANUAL_SSELECT_OPTION   0x10


XSpi_SetOptions(&MY_Spi,(XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION));


xspi_l.h

#define XSP_CR_LOOPBACK_MASK        0x1   /* Local loopback mode */
#define XSP_CR_ENABLE_MASK          0x2   /* System enable */
[b]#define XSP_CR_MASTER_MODE_MASK     0x4   /* Enable master mode */[/b]
[b]#define XSP_CR_CLK_POLARITY_MASK    0x8   /* Clock polarity high or low */[/b]
#define XSP_CR_CLK_PHASE_MASK      0x10   /* Clock phase 0 or 1 */
#define XSP_CR_TXFIFO_RESET_MASK   0x20   /* Reset transmit FIFO */
#define XSP_CR_RXFIFO_RESET_MASK   0x40   /* Reset receive FIFO */
#define XSP_CR_MANUAL_SS_MASK      0x80   /* Manual slave select assertion */
#define XSP_CR_TRANS_INHIBIT_MASK  0x100  /* Master transaction inhibit */



XSpi_mSetControlReg(XPAR_OPB_SPI_0_BASEADDR, (XSP_CR_ENABLE_MASK | XSP_CR_MASTER_MODE_MASK));

/* The following address types are used when setting and getting the addresses
* of the driver. These are mutually exclusive such that only one or the other
* may be specified.
*/
/** bus address of slave device */
#define XII_ADDR_TO_SEND_TYPE       1
/** this device's bus address when slave */
#define XII_ADDR_TO_RESPOND_TYPE    2

#include "xparameters.h"
#include "xiic.h"
#include "xiic_l.h"
#include "xbasic_types.h"
#include "xstatus.h"      

#define XI2C_ADDRESS_TO_SEND        0x01

void IIC_init(XIic MY_Iic)
{
Xuint32 Iic_status;
XIic_Initialize  (&MY_Iic, XPAR_OPB_IIC_0_DEVICE_ID);
//XIic_SetOptions (&MY_Iic,XIIC_CR_ENABLE_DEVICE_MASK);
XIic_Start(&MY_Iic);
/*
Iic_status= XIic_SelfTest(&MY_Iic);
    if(Iic_status== XST_SUCCESS){
        xil_printf("IIC selftest succesful \r\n");
      }
      else{      
       xil_printf("IIC some errors detected \r\n");
        }
*/
}

void main(void)
{      
       while(1)
          {
            XIic_SetAddress(&MY_Iic, XII_ADDR_TO_SEND_TYPE, XI2C_ADDRESS_TO_SEND);        
            XIic_MasterSend (&MY_Iic,0x55,1);  
          }
            
}