portRESTORE_CONTEXT MACRO

; Set the LR to the task stack.                                     
    LDR        R1, =pxCurrentTCB
    LDR        R0, [R1]
    LDR        LR, [R0]

; The critical nesting depth is the first item on the stack.     
; Load it into the ulCriticalNesting variable.                     
    LDR        R0, =ulCriticalNesting
    LDMFD    LR!, {R1}
    STR        R1, [R0]

; Get the SPSR from the stack.                                     
    LDMFD    LR!, {R0}
    MSR        SPSR_cxsf, R0

; Restore all system mode registers for the task.                 
    LDMFD    LR, {R0-R14}^
    NOP

; Restore the return address.                                     
    LDR        LR, [LR, #+60]

; And return - correcting the offset in the LR to obtain the     
; correct address.                                                 
    SUBS    PC, LR, #4

    ENDM

ДО
SP=0xFEA4
LR=0x34EC
0x34EC-0x3527:
00 00 00 00 01 01 01 01 02 02 02 02 03 03 03 03 04 04 04 04 05 05 05 05 06 06 06 06 07 07 07 07 08 08 08 08 09 09 09 09 10 10 10 10 11 11 11 11 12 12 12 12 28 35 00 00 aa aa aa aa

portRESTORE_CONTEXT
  000001F4  E8DE7FFF  LDMIA        LR, {R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,SP,LR}^

ПОСЛЕ
SP=0xFEA4
LR=0x34EC

ДО
SP=0x3290
LR=0x40CC
0x40CC-0x412C:
00 00 00 00 01 01 01 01 02 02 02 02 03 03 03 03 04 04 04 04 05 05 05 05 06 06 06 06 07 07 07 07 08 08 08 08 09 09 09 09 10 10 10 10 11 11 11 11 12 12 12 12 08 41 00 00 aa aa aa aa

portRESTORE_CONTEXT
  0000232C  E8DE7FFF  LDMIA        LR, {R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,SP,LR}^

ПОСЛЕ
SP=0x4108
LR=0xAAAAAAAA

       MODULE       ?program_start
    SECTION       IRQ_STACK:DATA:NOROOT(3)
                SECTION       FIQ_STACK:DATA:NOROOT(3)
                SECTION       UND_STACK:DATA:NOROOT(3)
                SECTION       ABT_STACK:DATA:NOROOT(3)        
                SECTION       SVC_STACK:DATA:NOROOT(3)
                SECTION       CSTACK:DATA:NOROOT(3)
                SECTION    .text:CODE:NOROOT(2)
                PUBLIC     __iar_program_start
                EXTERN  ?main
                CODE32
                

__iar_program_start:
        NOP  ; execute some instructions to access CPU registers after wake
        NOP  ; up from Reset, while waiting for OSC stabilization
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
; --- Initialize Stack pointer registers
      ; Enter each mode in turn and set up the stack pointer
           MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit   ; No interrupts
           LDR     SP, =SFE(FIQ_STACK)

           MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit   ; No interrupts
           LDR     SP, = SFE(IRQ_STACK)

           MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit   ; No interrupts
           LDR     SP, = SFE(ABT_STACK)
    
           MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit   ; No interrupts
        LDR     SP, = SFE(UND_STACK)

           MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit   ; No interrupts
           LDR     SP, = SFE(SVC_STACK)
; --- Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
        MOV     r0, #0x60000            
        MCR     p15,0x1,r0,c15,c1,0
; --- Now change to USR/SYS mode and set up User mode stack,
        MSR     CPSR_c, #Mode_SYS              ; IRQs & FIQs are now enabled
        LDR     SP, = SFE(CSTACK)
; --- Now enter the C code
        B       ?main   ; Note : use B not BL, because an application will
                        ; never return this way
        LTORG
        END

IMPORT  __iar_program_start
        SECTION    .intvec:CODE(2)    ;<- эта секция расположена с 0 адреса         
        CODE32
;*******************************************************************************
;                      Import exception handlers
;*******************************************************************************
        IMPORT  Undefined_Handler
        IMPORT  SWI_Handler
        IMPORT  Prefetch_Handler
        IMPORT  Abort_Handler
        IMPORT  FIQ_Handler
;*******************************************************************************
;            Export Peripherals IRQ handlers table address
;*******************************************************************************

;*******************************************************************************
;                        Exception vectors
;*******************************************************************************

        LDR     PC, Reset_Addr
        LDR     PC, Undefined_Addr
        LDR     PC, SWI_Addr
        LDR     PC, Prefetch_Addr
        LDR     PC, Abort_Addr
        NOP                            ; Reserved vector
        LDR     PC, IRQ_Addr
    LDR    PC, FIQ_Addr
;*******************************************************************************
;               Exception handlers address table
;*******************************************************************************
Reset_Addr      DCD     __iar_program_start
Undefined_Addr  DCD     UndefinedHandler
SWI_Addr        DCD     SWIHandler
Prefetch_Addr   DCD     PrefetchAbortHandler
Abort_Addr      DCD     DataAbortHandler
                DCD     0               ; Reserved vector
IRQ_Addr        DCD     IRQHandler
FIQ_Addr    DCD     FIQ_Handler       ; Branch to fiq_handler

       LTORG

       END