Две комбинаторные логические функции (не сумматор) описаны с использованием CARRY_SUM буферов. Если девайсами установлены что-либо из ACEX1 или Cyclone, синтезатор не игнорирует эти буферы и все получается, как задумано, а если CycloneII – игнорирует и синтезит эти две функции на отдельных ячейках. Никакими средствами пока не удалось уговорить QII 7.1SP1. Разумеется, логическая опция Ignore CARRY Buffers = Off.

Попробуйте законстрейнить путь, по которому идет перенос. Вам же по сути не размещение нужно, а скорость переноса. Задайте ограничение по времени на этот сигнал, синтезатор вынужден будет сам оптимизировать размещение.

По мере ужесточения констрейна по времени распространения, QII ужимал тайминг без использования переноса, а затем сдался, но так и не задействовал перенос.

Моя переписка с Альтерой по этому поводу

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Request No: 10563516 Status: Closed
Date Opened (PDT): 10/9/2006 05:48 PM
Date Closed (PDT): 10/20/2006 02:11 AM
Device Family: CYCLONE II Device: EP2C5Q208I8N
Request Title: Quartus II Synthesizer ignores carry chains
for Cyclone II family
Steps to Reproduce
/ Description: My software is Quartus II build 202 SP1

I have written the simple AHDL module (the 8-bit comparator)
(AHDL text placed at the end of the letter).

When I try to implement this module into Cyclone II device
(e.g. EP2C5),
the Quartus II Synthesizer reports me that "Ignored 8 CARRY
buffer(s)", and the fitter builds the logic without
carry-chain.

When I try to implement this module into Cyclone or Acex1K
device,
the synthesizer accepts my logic "as is", i.e. builds the
carry-chain logic.

In the project option/assignments I change ONLY target
device. If I try to implement a simple LPM_COUNTER instead
of my module with the same options in the same project, the
synthesizer and fitter implement the carry-chain
independently of device family.

How can I force the Quartus II software to build the
carry-chain logic in my module?

Thank you in advance.

subdesign cmp_8
(
A[7..0] : input;
B[7..0] : input;
EQ : output;
)

variable
cry[7..0] : carry;
begin
cry[].in = ( A[] !$ B[] ) & (Cry[6..0].out, vcc);
EQ = cry[7].out;
end;


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10/10/2006 01:27 AM To Customer Hi,

This is a software bug. It will be corrected in the future
release. You could implement a comparator in Verilog/VHDL,
but whether the comparator use carry chain or not dependent
on the comparator writing style. Please refer to a
comparator example in attachment.

Best regards,
Harold


module carrychain(input [7:0] a,input [7:0] b, output eq);
wire [8:0] c;
assign c = {1'b0,a} - {1'b0,b};
assign eq = c[8];

//assign eq = (a==;
//this kind of style is not using carry chain,but implemented in more less LEs.
endmodule

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2/18/2007 09:58 PM To Customer Hi Dmitry,

Thanks for using MySupport.

I have searched the related database. It is a regret that
this issue is not in top priority since Verilog and VHDL
have supported carry chain implementation.

If the carry chain block is just a sub-module in your whole
design, you could use Verilog/VHDL for this sub-module, and
Quartus II can support mixed language.

Thank you and have a nice day.

Best Regards,
Amanda


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2/19/2007 03:14 PM From Customer
You wrote:

> It is a regret that this issue is not in top priority
since Verilog and
> VHDL have supported carry chain implementation

Not quite

The new example (verilog) is placed at the end of the
letter. When I fit this module into Cyclone device, Quartus
II builds carry-chain; when I change the target device to
Cyclone II, Quartus II ignores carry-chain.

This module is the fast multiplexer. I want that this module
work AS FAST AS POSSIBLE (i.e. with carry!!!). AS I WROTE on
Verilog and AHDL! No pipeline is possible. No additional
LCELLs are possible.

This is offensive that your device (Cyclone II) can give me
that I want (according to datasheet), but your software
can't properly implement my simple construction into
Cyclone II chip.

How can I get WHAT I WANT, by means of ANY language?


module mx_4_1
(
input [3:0] D,
input [3:0] Sel,
output O
);

wire [3:0] Si;
wire [3:0] Ci;
wire [3:0] Co;
wire [3:0] So;

carry_sum Cry0
(.sin(Si[0]),.cin(Ci[0]),.sout(So[0]),.cout(Co[0]));
carry_sum Cry1
(.sin(Si[1]),.cin(Ci[1]),.sout(So[1]),.cout(Co[1]));
carry_sum Cry2
(.sin(Si[2]),.cin(Ci[2]),.sout(So[2]),.cout(Co[2]));
carry_sum Cry3
(.sin(Si[3]),.cin(Ci[3]),.sout(So[3]),.cout(Co[3]));

assign Si[2:0] = 0;
assign Ci[3] = 0;

assign Ci[0] = D[0] & Sel[0];
assign Ci[1] = (D[1] & Sel[1]) | Co[0];
assign Ci[2] = (D[2] & Sel[2]) | Co[1];
assign Si[3] = (D[3] & Sel[3]) | Co[2];

assign O = So[3];

endmodule

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******

2/20/2007 11:54 PM To Customer Hi Dmitry,

I am sorry for the last confused reply. With the codes you
sent, I can reproduce the issue you mentioned.

After discussing with related people. This issue is caused
by two reasons. One is software reason, and a new bug report
has been issued. It is planed to fix in Quartus II 7.2.

Another is the hardware reason ---- the different structures
between Cyclone and Cyclone II. In fact, Cyclone’s carry
chain has better performance than Cyclone II’s. This is a
known issue of Cyclone II. For more information about the
carry chain, you could refer to the following links:
Page 6~7 of
http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf

page 8~10 of
http://www.altera.com/literature/hb/cyc/cyc_c51002.pdf

You can see that the carry chain in Cyclone II is shorter
than the one in Cyclone device. It makes software difficult
to implementing carry chain in Cyclone II.

If carry chain is a very important feature of your design,
we suggest you to use Cyclone device.

Sorry about this confusion, and thanks a lot for notifying
us about this. Currently, there is no workaround in Cyclone
II. If you encounter difficulty to meet performance of your
deisgn, we can help you from other aspects. For doing this,
we need the project file and the performance requirement.

Best Regards,
Amanda

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******

2/21/2007 03:24 PM From Customer Hi Amanda,

Thank you for elucidation.

Now I know that this problem can't be solved using current
version of Quartus II, independently of language I write...

>You can see that the carry chain in Cyclone II is shorter
than the one in
>Cyclone device.

The length of carry-chain is not so important, I seldom use
>16.
Possibility of use the carry-chains where I want - that is
just the point.

I'll be waiting for new release of Quartus II software.

Best Regards,
Dmitry


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******

2/21/2007 07:01 PM To Customer Hi Dmitry,

You are right that the length of carry chain is not the
excuse of the software issue. But it is the cause of the
bug. Related people are working on it.

The fix is planned in Quartus II 7.2.

I will set close-pending for this SR, and it will be closed
in couple of days if without update. If you have other
questions regarding our products, please issue a new one,
and a right people will work with you.

Thank you and have a nice day!

Best Regards,
Amanda

Благодарю, _LD! Вы избавили меня от подобной переписки с сапортом. Было у меня две гипотезы на эту тему: 1- баг QII (таки да!); 2 – LUT CycloneII в арифметическом режиме не поддерживают всех возможных логических функций трех переменных. Последняя возникла, как следствие реализации переноса синтезатором, как только логика была идентична сумматору. Но это удалось проверить, так что уже думал писать в сапорт, хотя опыт общения с ними исключительно отрицательный, чего не скажешь о Вашем запросе.

Когда-то я уже имел подобную проблему, правда, задача синтезатору была еще сложнее: компаратор с двумя выходами: больше и равно, - реализовать на одном наборе ячеек с использованием переноса и каскадирования в ACEX1K. QII не справился, а MAX+PLUSII – смог! Надеется на новую версию QII смысла не было, поскольку в новых семействах от каскадирования отказались, а в поддержку стареющего ACEX1K не инвестировали.

QII 7.2 уже официально объявлен, так что, как говорил Верещагин (к/ф «Белое солнце …»), давая прикурить зажженной толовой шашкой: «Посмотрим - какой это Сухов».