DFChipSelect();

    AT91F_PDC_DisableRx(pPdc);
    AT91F_PDC_SetRx(pPdc, (char *) &(), bCmdSize);
    AT91F_PDC_SetNextRx(pPdc, pData, dDataSize);

    AT91F_PDC_DisableTx(pPdc);    
    AT91F_PDC_SetTx(pPdc, (char *) &(pDataFlash->commandS), bCmdSize);
    AT91F_PDC_SetNextTx(pPdc, pData, dDataSize);

    AT91F_PDC_EnableRx(pPdc);
    AT91F_PDC_EnableTx(pPdc);

void InitSPI(void)
{
AT91F_SPI_CfgPMC();

AT91F_SPI_Reset(ptrSPI);

*AT91C_PIOA_PER = AT91C_PIO_PA11|AT91C_PIO_PA10;

*AT91C_PIOA_OER = AT91C_PIO_PA11|AT91C_PIO_PA10;// |  // CS

    AT91F_PIO_CfgPeriph(
        AT91C_BASE_PIOA, // PIO controller base address
        ((unsigned int) AT91C_PA13_MOSI    ) |
        ((unsigned int) AT91C_PA14_SPCK    ) |    
        ((unsigned int) AT91C_PA12_MISO    ), 0);
    
AT91C_PA10_NPCS2;

csADC1high;

csFLASHhigh;

AT91F_SPI_CfgMode(ptrSPI, AT91C_SPI_MSTR |   AT91C_SPI_MODFDIS |   |  (0x0F<<16)  );
AT91F_SPI_CfgCs(ptrSPI, 0,  AT91C_SPI_CPOL|    ( (MCK/SPI_CLOCK) << 8)   );

ptrSPI->SPI_CR = AT91C_SPI_SPIEN;

(unsigned short)ptrSPI->SPI_RDR;
(unsigned short)ptrSPI->SPI_SR;
(unsigned short)ptrSPI->SPI_RDR;

AT91F_SPI_CfgPCS(ptrSPI, 0x0E);
}


#define csFLASHhigh *AT91C_PIOA_SODR = AT91C_PIO_PA10
#define csFLASHlow *AT91C_PIOA_CODR = AT91C_PIO_PA10

{
csFLASHlow;
csADC1high;

Buf[0]=0xD7;
Buf[1]=0xFF;
Buf[2]=0xFF;
Buf[3]=0xFF;
Buf[4]=0xFF;
Buf[5]=0xFF;

Bufr[0]=AT91_spi(Buf[0]);
Bufr[1]=AT91_spi(Buf[1]);
Bufr[2]=AT91_spi(Buf[2]);
Bufr[3]=AT91_spi(Buf[3]);
Bufr[4]=AT91_spi(Buf[4]);
Bufr[5]=AT91_spi(Buf[5]);

Bufr[6]=0;

USART0_SendData(Bufr,7);

csFLASHhigh;

}

unsigned char AT91_spi(unsigned char bsend)
{
while( !(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TDRE )){;}
// wait until all transfers are completed
AT91C_BASE_SPI->SPI_TDR =(unsigned short)  bsend;
//transmit
while( !(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TDRE )){;}
// wait for received char
return (unsigned char)( AT91C_BASE_SPI->SPI_RDR );
}