Идея в том, чтоб описать 8-битный стек, запись и чтение производится с помощью управляющего сигнала "wr"
Код
module stack(out_stack, in_stack);
output [7:0] out_stack;
input [7:0] in_stack;
wire st0 [7:0],
st1 [7:0],
st2 [7:0],
st3 [7:0],
st4 [7:0],
st5 [7:0],
st6 [7:0],
st7 [7:0];
wire wr;
always in_stack
if (wr)
st7 = st6;
st6 = st5;
st5 = st4;
st4 = st3;
st3 = st2;
st2 = st1;
st1 = st0;
st0 = in_stack;
endmodule
при компиляции выдает данное сообщение
Цитата
# Pass 1. Scanning modules hierarchy.
# Error: VCP2000 stack.v : (20, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Error: VCP2000 stack.v : (21, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Error: VCP2000 stack.v : (22, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Error: VCP2000 stack.v : (23, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Error: VCP2000 stack.v : (24, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Error: VCP2000 stack.v : (25, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Error: VCP2000 stack.v : (26, 8): Syntax error. Unexpected token: =. Expected tokens: '#' , '(' , ':' , 'delay' , ',' ... .
# Warning: VCP2515 stack.v : (21, 1): Undefined module: st4 was used. Port connection rules will not be checked at such instantiations.
# Warning: VCP2515 stack.v : (20, 1): Undefined module: st5 was used. Port connection rules will not be checked at such instantiations.
# Warning: VCP2515 stack.v : (23, 1): Undefined module: st2 was used. Port connection rules will not be checked at such instantiations.
# Warning: VCP2515 stack.v : (22, 1): Undefined module: st3 was used. Port connection rules will not be checked at such instantiations.
# Warning: VCP2515 stack.v : (26, 1): Undefined module: in_stack was used. Port connection rules will not be checked at such instantiations.
# Warning: VCP2515 stack.v : (25, 1): Undefined module: st0 was used. Port connection rules will not be checked at such instantiations.
# Warning: VCP2515 stack.v : (24, 1): Undefined module: st1 was used. Port connection rules will not be checked at such instantiations.
# Compile failure 7 Errors 7 Warnings Analysis time : 0[s].
# done
не могу понять что я делаю не так...
Заранее спасибо за помощь.)
если не туда разместил тему перенесите пожалуйста в нужный раздел форума
Описание стека на Verilog, подскажите что не так
Mar 13 2008, 07:27
