library ieee;
use ieee.std_logic_1164.all;

library unisim;
use unisim.vcomponents.all;

entity delay is
    port(
        i     : in  std_logic;
        o    : out std_logic
    );
end delay;


architecture delay of delay is

attribute noopt : boolean;
attribute noopt of xlut0    : label is TRUE;
attribute noopt of xlut1    : label is TRUE;

attribute rloc: string;
attribute rloc of xlut0        : label is "X0Y0";
attribute rloc of xlut1        : label is "X0Y0";

component LUT1
-- synthesis translate_off
generic (
INIT : bit_vector := X"2");
-- synthesis translate_on
port (    
        O : out STD_ULOGIC;
        I0 : in STD_ULOGIC);
end component;

attribute INIT : string;
attribute INIT of xlut0 : label is "2";
attribute INIT of xlut1 : label is "2";

signal s0, s1    : std_logic;

begin
    
xlut0: LUT1
-- synthesis translate_off
generic map(
INIT => x"2" ) -- режим буфера
-- synthesis translate_on
port map (O => s0, I0 => i);

xlut1: LUT1
-- synthesis translate_off
generic map(
INIT => x"2" ) -- режим буфера
-- synthesis translate_on
port map (O => s1, I0 => s0);

o<=s1;

end s_delay;