-- SyncRo
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SyncRo is
   port(
       Clk  : in    std_logic;
       ClkIn   : in    std_logic;
 Reset    : in    std_logic;
       D       : in    std_logic;
       Q       : out   std_logic;
       E       : out   std_logic
 );
   end SyncRo;

architecture default of SyncRo is

signal r1, r2, dd   : std_logic;

begin

ClkInProc: process (Reset, ClkIn)
begin
if(Reset='1') then
   r1<='0';
   dd<='0';
elsif(r2='1') then
   r1<='0';
elsif(ClkIn = '1' and ClkIn'event) then
   r1<='1';
   dd<=D;
end if;
end process;

ClkProc: process (Reset, Clk)
begin
if(Reset='1') then
   r2<='0';
elsif(Clk = '1' and Clk'event) then
   r2<=r1;
end if;
end process;

Q<=dd;
E<=r2;

end default;