typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
typedef struct _AT91S_CKGR {
    AT91_REG     CKGR_MOR;     // Main Oscillator Register
    AT91_REG     CKGR_MCFR;     // Main Clock  Frequency Register
    AT91_REG     Reserved0[1];     //
    AT91_REG     CKGR_PLLR;     // PLL Register
} AT91S_CKGR, *AT91PS_CKGR;
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
#define     AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
#define     AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
#define     AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define     AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define     AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define     AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
#define     AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define     AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define     AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4

#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR)     0xFFFFFC20) // (CKGR) Base Address

// использование:

void Test()
{
    AT91C_BASE_CKGR->CKGR_MOR = AT91C_CKGR_MOSCEN | AT91C_CKGR_DIV_0 | AT91C_CKGR_USBDIV_0;
}

#ifndef AT91SAM9260_H
#define AT91SAM9260_H

#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
        AT91_REG         SDRAMC_MR;     // SDRAM Controller Mode Register
        AT91_REG         SDRAMC_TR;     // SDRAM Controller Refresh Timer Register
        AT91_REG         SDRAMC_CR;     // SDRAM Controller Configuration Register
        AT91_REG         SDRAMC_HSR;    // SDRAM Controller High Speed Register
        AT91_REG         SDRAMC_LPR;    // SDRAM Controller Low Power Register
        AT91_REG         SDRAMC_IER;    // SDRAM Controller Interrupt Enable Register
        AT91_REG         SDRAMC_IDR;    // SDRAM Controller Interrupt Disable Register
        AT91_REG         SDRAMC_IMR;    // SDRAM Controller Interrupt Mask Register
        AT91_REG         SDRAMC_ISR;    // SDRAM Controller Interrupt Mask Register
        AT91_REG         SDRAMC_MDR;    // SDRAM Memory Device Register
        AT91_REG         Reserved0[118];        //
        AT91_REG         SMC_SETUP0;    //  Setup Register for CS 0
        AT91_REG         SMC_PULSE0;    //  Pulse Register for CS 0
        AT91_REG         SMC_CYCLE0;    //  Cycle Register for CS 0
        AT91_REG         SMC_CTRL0;     //  Control Register for CS 0
        AT91_REG         SMC_SETUP1;    //  Setup Register for CS 1
        AT91_REG         SMC_PULSE1;    //  Pulse Register for CS 1
        AT91_REG         SMC_CYCLE1;    //  Cycle Register for CS 1
        AT91_REG         SMC_CTRL1;     //  Control Register for CS 1
        AT91_REG         SMC_SETUP2;    //  Setup Register for CS 2
        AT91_REG         SMC_PULSE2;    //  Pulse Register for CS 2
        AT91_REG         SMC_CYCLE2;    //  Cycle Register for CS 2
        AT91_REG         SMC_CTRL2;     //  Control Register for CS 2
        AT91_REG         SMC_SETUP3;    //  Setup Register for CS 3
        AT91_REG         SMC_PULSE3;    //  Pulse Register for CS 3
        AT91_REG         SMC_CYCLE3;    //  Cycle Register for CS 3
        AT91_REG         SMC_CTRL3;     //  Control Register for CS 3
        AT91_REG         SMC_SETUP4;    //  Setup Register for CS 4
        AT91_REG         SMC_PULSE4;    //  Pulse Register for CS 4
        AT91_REG         SMC_CYCLE4;    //  Cycle Register for CS 4
        AT91_REG         SMC_CTRL4;     //  Control Register for CS 4
        AT91_REG         SMC_SETUP5;    //  Setup Register for CS 5
        AT91_REG         SMC_PULSE5;    //  Pulse Register for CS 5
        AT91_REG         SMC_CYCLE5;    //  Cycle Register for CS 5
        AT91_REG         SMC_CTRL5;     //  Control Register for CS 5
        AT91_REG         SMC_SETUP6;    //  Setup Register for CS 6
        AT91_REG         SMC_PULSE6;    //  Pulse Register for CS 6
        AT91_REG         SMC_CYCLE6;    //  Cycle Register for CS 6
        AT91_REG         SMC_CTRL6;     //  Control Register for CS 6
        AT91_REG         SMC_SETUP7;    //  Setup Register for CS 7
.............

#include "AT91SAM9260.h"
#include <stdio.h>

int main()
{
    printf("PMC_SCSR=%X\n", AT91C_BASE_PMC);
    printf("PMC_SCSR=%X\n", AT91C_BASE_PMC->PMC_SCDR);//Тута будет БАБАХ!!!!!
    return 0;
}

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