Вот как надо и все работает непрерывно в два буффера попеременно
#include "cpu.h"
volatile unsigned short *adc_buffers; volatile unsigned char adc_current_buffer=0; /// volatile unsigned char adc_samples=0; volatile unsigned char adc_num_channels=0;
char s[32]; void adc_interupt_irq(void) __irq { unsigned int status = AT91C_BASE_ADC->ADC_SR; int i; int k=0; int flg=0; AT91F_PDC_SetNextRx(AT91C_BASE_PDC_ADC, (char *)&adc_buffers[adc_current_buffer*adc_samples/2], adc_samples*sizeof(unsigned short)/4); // çàðÿæàåì âòîðîé áóôåð if(adc_current_buffer==0) adc_current_buffer = 1; else adc_current_buffer=0; // Delay(10); // lsd_clear_screen() ;
sprintf(s,"%d",adc_buffers[0]);
for(i=0;i<128;i++) { // if(adc_buffers2[i]>120 || adc_buffers2[i]<132) // if(adc_buffers2[i]<adc_buffers2[i+1]) // flg=1; // if(flg) lcd_set_pixel(i,(adc_buffers[i])/8,0x0000); }
// lcd_set_str(s,32,32,0,0xFFFFFF, 0x000000) ;
AT91C_BASE_AIC->AIC_EOICR = status; //âàø êîä }
/// Èíèöèàëèçàöèÿ ÀÖÏ void adc_init(volatile unsigned short *buffers,unsigned short samples,unsigned char channels)
{ adc_buffers = buffers; adc_samples = samples/2; adc_current_buffer = 0; AT91C_BASE_ADC->ADC_MR = 0;
/// Ìàòåìàòèêà êðàñèâî ïîëó÷èëàñü
//adc_num_channels = channels;
AT91C_BASE_ADC->ADC_CHER = AT91C_ADC_CH7;//channels;
/// ADCClock = 47.9232 / (7+1)*2 = 2.9952 Mhz AT91C_BASE_ADC->ADC_MR =(AT91C_ADC_SHTIM & (3<<24)) | (AT91C_ADC_STARTUP & (8 << 16)) | (AT91C_ADC_PRESCAL & (7<<8)) //3F | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_LOWRES_8_BIT | AT91C_ADC_TRGSEL_TIOA0 | AT91C_ADC_TRGEN_EN;
// çàðÿæàåì ïåðâûé áóôåð AT91F_PDC_SetRx(AT91C_BASE_PDC_ADC, (char*)&adc_buffers[adc_current_buffer*adc_samples], (adc_samples*sizeof(unsigned short)) ); adc_current_buffer = 1;
// çàðÿæàåì âòîðîé áóôåð AT91F_PDC_SetNextRx(AT91C_BASE_PDC_ADC, (char*)&adc_buffers[(adc_current_buffer*adc_samples)/2], (adc_samples*sizeof(unsigned short)) );
AT91F_PDC_EnableRx(AT91C_BASE_PDC_ADC); AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_TC0; // Enable clock to TC0 // 47.9232/AT91C_TC_CLKS_TIMER_DIV1_CLOCK[/2] = 23.9616 Mhz AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK|AT91C_TC_WAVESEL_UP_AUTO|AT91C_TC_WAVE|AT91C_TC_A CPA_SET|AT91C_TC_ACPC_CLEAR; AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // Enable timer AT91C_BASE_TC0->TC_RC = 768; AT91C_BASE_TC0->TC_RA = AT91C_BASE_TC0->TC_RC>>1; ///meander
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_ADC, AT91C_AIC_PRIOR_HIGHEST, AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE , (void *)adc_interupt_irq); AT91C_BASE_ADC->ADC_IER = AT91C_ADC_ENDRX; // IRQ enable, end of receive buffer AT91C_BASE_AIC->AIC_IECR = 1 << AT91C_ID_ADC; // Enable interrupt in AIC AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG; // Start timer };
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