//38.4kbps nastroyki dlya  26.000 433,92
    halSpiWriteReg(CCxxx0_FSCTRL1,  0x06);
    halSpiWriteReg(CCxxx0_FSCTRL0,  0x00);
    halSpiWriteReg(CCxxx0_FREQ2,    0x10);
    halSpiWriteReg(CCxxx0_FREQ1,    0xB0);  
    halSpiWriteReg(CCxxx0_FREQ0,    0x71);  
   halSpiWriteReg(CCxxx0_MDMCFG4,  0xCA);
   halSpiWriteReg(CCxxx0_MDMCFG3,  0x83);
   halSpiWriteReg(CCxxx0_MDMCFG2,  0x13);//GFSK
    halSpiWriteReg(CCxxx0_MDMCFG1,  0xA2);  //A2-with FEC
   halSpiWriteReg(CCxxx0_MDMCFG0,  0xF0);
    halSpiWriteReg(CCxxx0_CHANNR,   0x00);
    halSpiWriteReg(CCxxx0_DEVIATN,  0x34);
    halSpiWriteReg(CCxxx0_FREND1,   0x56);
    halSpiWriteReg(CCxxx0_FREND0,   0x10);
    halSpiWriteReg(CCxxx0_MCSM0 ,   0x18 );
   halSpiWriteReg(CCxxx0_FOCCFG,   0x16);
    halSpiWriteReg(CCxxx0_BSCFG,    0x6C);
    halSpiWriteReg(CCxxx0_AGCCTRL2, 0x43);
    halSpiWriteReg(CCxxx0_AGCCTRL1, 0x40);
    halSpiWriteReg(CCxxx0_AGCCTRL0, 0x91);  
    halSpiWriteReg(CCxxx0_FSCAL3,   0xE9);
    halSpiWriteReg(CCxxx0_FSCAL2,   0x2A);
    halSpiWriteReg(CCxxx0_FSCAL1,   0x00);
    halSpiWriteReg(CCxxx0_FSCAL0,   0x1F);
    halSpiWriteReg(CCxxx0_FSTEST,   0x59);
    halSpiWriteReg(CCxxx0_TEST2,    0x81);
    halSpiWriteReg(CCxxx0_TEST1,    0x35);
    halSpiWriteReg(CCxxx0_TEST0,    0x09);
    halSpiWriteReg(CCxxx0_IOCFG2,   0x40);
    halSpiWriteReg(CCxxx0_IOCFG0,   0x06);  
    halSpiWriteReg(CCxxx0_PKTCTRL1, 0x0C);
    halSpiWriteReg(CCxxx0_PKTCTRL0, 0x04);
    halSpiWriteReg(CCxxx0_ADDR,     addr);
    halSpiWriteReg(CCxxx0_PKTLEN,   0x08);

POWER_UP_RESET_CCxxx0();
  halRfWriteRfSettings();
  halSpiWriteReg(CCxxx0_FIFOTHR, 0x07);
  halSpiWriteReg(CCxxx0_PATABLE, paTable);
  halSpiWriteReg(CCxxx0_SYNC1, 0x9B);
  halSpiWriteReg(CCxxx0_SYNC0, 0xAD);
  halSpiStrobe(CCxxx0_SIDLE);  
  halSpiStrobe(CCxxx0_SFRX);
  halSpiStrobe(CCxxx0_SFTX);

CC1100_writestrobe(CC1100_SRES);
CC1100_burstwrite(0x00, CC1100_configuration, 47);
CC1100_burstwrite(CC1100_PATABLE, paTable, 1);

static const U08 rf_config_tbl[] =
{
    /* IOCFG2   */  IO_INV_DIS                 |    /* G2 invert disable */
                    IO_FUNC_RX_FIFO_1,              /* G2 mode - FIFO    */

    /* IOCFG1   */  IOCFG1_DRIVE_STRENGTH_LOW  |    /* GPIO output strength low */
                    IO_INV_DIS                 |    /* G1 invert disable        */
                    IO_FUNC_Z_STATE,                /* G1 mode - SDO            */

    /* IOCFG0   */  IOCFG0_TEMP_SENS_DIS       |    /* Temp sensor disable  */
                    IO_INV_DIS                 |    /* G0 invert disable    */
                    IO_FUNC_SYNC,                   /* G0 mode - SYNC       */

    /* FIFOTHR  */  FIFOTHR_TX_33_RX_32,

    /* SYNC1    */  SYNK1_DEFAULT,                  /* Synk chunk = 0xD391  */
    /* SYNC0    */  SYNK0_DEFAULT,

    /* PKTLEN   */  1,                              /* Startup packet length */

    /* PKTCTRL1 */  PKTCTRL1_PQT_1             |
                    PKTCTRL1_CRC_AUTOFLUSH_EN  |    /* Autoflush fault packet    */
                    PKTCTRL1_APPEND_STATUS_DIS |    /* Status bytes not appended */
                    PKTCTRL1_ADR_CHK_EN_BK_0_255,   /* Enable address checking   */

    /* PKTCTRL0 */  PKTCTRL0_WHITE_DATA_EN     |
                    PKTCTRL0_PKT_FORMAT_NORM   |
                    PKTCTRL0_CC2400_DIS        |
                    PKTCTRL0_CRC_EN            |
                    PKTCTRL0_LENGTH_CONFIG_FIX,

    /* ADDR     */  0x55,

    /* CHANNR   */  RF_CHANNEL_DEF,

    /* FSCTRL1  */  12,                             /* FIF = 304.62 kHz (from SRFS) */

    /* FSCTRL0  */  0,                              /* Freq offset = 0 */

    /* FREQ2    */  0x5C,                           /* 0 channel freq = 2400.499908 */
    /* FREQ1    */  0x53,
    /* FREQ0    */  0xB1,

    /* MDMGFG4  */  MDMCFG4_CHANBW_E_0         |    /* RX channel bandwidth = 812.5 kHz */
                    MDMCFG4_CHANBW_M_0         |
                    MDMCFG4_DRATE_E_14,             /* Data Rate = 499.877930 kbit */

    /* MDMGFG3  */  59,

    /* MDMGFG2  */  MDMCFG2_DEM_DCFILT_EN      |
                    MDMCFG2_MOD_FORMAT_MSK     |
                    MDMCFG2_MANCHESTER_DIS     |
                    MDMCFG2_SYNC_MODE_30_32,

    /* MDMGFG1  */  MDMCFG1_FEC_DIS            |
                    MDMCFG1_NUM_PREAMBLE_8     |
                    MDMCFG1_CHANSPC_E_3,            /* Channel space = 249.938 kHz */

    /* MDMGFG0  */  59,

    /* DEVIATN  */  DEVIATN_DEVIATION_E_0      |    /* Don't use deviations with MSK */
                    DEVIATN_DEVIATION_M_0,

    /* MCSM2    */  MCSM2_RX_TIME_RSSI_DIS     |
                    MCSM2_RX_TIME_QUAL_DIS     |
                    MCSM2_RX_TIME_2,

    /* MCSM1    */  MCSM1_CCA_MODE_RSSI        |
                    MCSM1_RXOFF_MODE_IDLE      |
                    MCSM1_TXOFF_MODE_RX,

    /* MCSM0    */  MCSM0_FS_AUTOCAL_FROM_IDLE |
                    MCSM0_PO_TIMEOUT_16        |
                    MCSM0_PIN_CTRL_DIS         |
                    MCSM0_XOSC_FORCE_ON_DIS,

    /* FOCCFG   */  0x1D,
    /* BSCFG    */  0x1C,

    /* AGCCTRL2 */  0xC7,
    /* AGCCTRL1 */  0x40,
    /* AGCCTRL0 */  0xB2,

    /* WOREVT1  */  0x87,
    /* WOREVT0  */  0x6B,
    /* WORCTRL  */  0xFC,

    /* FREND1   */  0x56,
    /* FREND0   */  0x10,

    /* FSCAL3   */  0xEA,
    /* FSCAL2   */  0x0A,
    /* FSCAL1   */  0x00,
    /* FSCAL0   */  0x19,

    /* RCCTRL1  */  0x41,
    /* RCCTRL0  */  0x00,

    /* FSTEST   */  0x59,
    /* PTEST    */  0x7F,
    /* AGCTEST  */  0x3F,
    /* TEST2    */  0x88,
    /* TEST1    */  0x31,
    /* TEST0    */  0x0B
};

/* ****** */

    RF_SEL();

    SSP_TX(0 | WRITE | BURST); csp_ssp_get();

    for (to = 0; to < sizeof(rf_config_tbl); to++)
    {
        SSP_TX(rf_config_tbl[to]);
        SSP_RX();
    }
    RF_DESEL();

/* ****** */