; ***************************************************************************
; * Cache and MMU Configuration

    [ {TRUE}
        mrc        p15, 0, r0, c1, c0, 0    ; read CP15 register 1 into r0
        bic        r0, r0, #0x01            ; clear MMU enable
        bic        r0, r0, #(0x01 << 0x0c)    ; disable I Cache
        bic        r0, r0, #(0x01 << 0x02)    ; disable D Cache
        mcr        p15, 0, r0, c1, c0, 0    ; write value back

        mov        r0, #0x00
        mcr        p15, 0, r0, c7, c7, 0    ; invalidate caches
        mcr        p15, 0, r0, c8, c7, 0    ; invalidate TLBs


        ldr        r0, =ttb_first_level    ; set start of Translation Table base (16k Boundary)
        mcr        p15, 0x00, r0, c2, c0, 0x00; write to CP15 register 2
;
; Create translation table for flat mapping
; Top 12 bits of VA is pointer into table
; Create 4096 entries from 000xxxxx to fffxxxxx
;
        mov        r1, #0x00                ; loop counter
        ldr        r2, =2_110111110010        ; set access permissions (AP) for full access SVC/USR (11:10)
                                        ; set for domain 15 (8:5)
                                        ; must be 1 (4)
                                        ; set non cachable non bufferable (CB) (3:2)
                                        ; set for 1Mb section (1:0)
init_ttb0
        orr        r3, r2, r1, lsl #0x14
        ldr        r4, =sections
init_ttb1
        ldr        r5, [r4], #0x04
        tst        r5, #0x01
        bne        init_ttb2
        cmp        r1, r5, lsr #0x14
        addlo    r4, r4, #0x08
        blo        init_ttb1
        ldr        r5, [r4], #0x04
        cmp        r1, r5, lsr #0x14
        addhs    r4, r4, #0x04
        bhs        init_ttb1
        ldr        r5, [r4]
        orr        r3, r3, r5
init_ttb2
        str        r3, [r0, r1, lsl #0x02]
        add        r1, r1, #0x01
        cmp        r1, #0x1000
        blo        init_ttb0
;
; Init domains
;
        mov        r0, #(2_01 << 0x1e)        ; must define behaviour for domain 15 (31:30), set client
        mcr        p15, 0x00, r0, c3, c0, 0x00; write to CP15 register 3
;
; Set global core configurations
;
        mrc        p15, 0x00, r0, c1, c0, 0x00; read CP15 register 1 into r0

        orr        r0, r0, #(0x01 << 0x0c)    ; enable I Cache
        orr        r0, r0, #(0x01 << 0x02)    ; enable D Cache
        orr        r0, r0, #0x01            ; enable MMU
;
; Additional configuration options      
;        
;        orr        r0, r0, #(0x01 << 0x0e)    ; enable Round Robin cache replacement
;        orr        r0, r0, #(0x01 << 0x0d)    ; enable Hi Vectors
        orr        r0, r0, #(0x01 << 0x01)    ; enable data address alignment checking

        mcr        p15, 0x00, r0, c1, c0, 0x00; write cp15 register 1
    ]

; ***************************************************************************
; *

sections
        DCD        0x00000000    ; SRAM
        DCD        0x00100000
        DCD        2_1100        ; wb, buffered

        DCD        0x20000000    ; SDRAM
        DCD        0x22000000
        DCD        2_1100        ; wb, buffered

        DCD        0x00000001    ; END

#ifdef __IAR_SYSTEMS_ICC__
__arm unsigned int AT91F_ARM_ReadControl(void)
{
return __MRC(15,0,ctl,1,0,0);
}
#else
__inline unsigned int AT91F_ARM_ReadControl()
{
register unsigned int ctl;
__asm("MRC p15, 0, ctl, c1, c0, 0");
return ctl;
}
#endif

return __MRC(15,0,1,0,0);