void Soft_Delay (DWORD N)
{
    volatile DWORD i;
    for (i=0; i<N; i++)
    {
       ;
    }
    return;
}

//******************************************************************************
//  GLOBAL    DEFINITIONS
//******************************************************************************
#define TIMER0_INT 0x00000010  

#define LED 0x00000400          // P0.10 pin

#define PRESCALE_VAL 0x0001869F // TC increments on every 100000 PCLK

#define MATCH_VAL 0x00000078    // Match on 120 value (decimal)

#define MATCH_CONFIG 0x0003     // Interrupt on MR0; Reset on MR0



//******************************************************************************
//  FUNCTION    PROTOTYPE
//******************************************************************************
__irq void FIQ_Handler (void);



//******************************************************************************
//  CODE
//******************************************************************************
int main()
{
    //Fosc = 12 MHz
    Init_PLL(0x42, 0x00); // CCLK = 2*Fosc = 24 MHz; PCLK = CCLK / 4 = 6 MHz
                                  
    IO0DIR=LED;    // Set P0.10 as output
    IO0SET=LED;  // initially turn OFF LED    

    Init_Timer(PRESCALE_VAL, MATCH_VAL, MATCH_CONFIG);
    Enable_Timer(0x00);        // Timer 0 enable    
                                                      
    VICIntSelect = TIMER0_INT; //assign TIMER0 intterupt to FIQ category
    VICIntEnable = TIMER0_INT; //Enable TIMER0 interrupt
    
    while(1)
    {
       ;
    }
}

//interupt handler function
__irq void FIQ_Handler (void)
{
    IO0CLR=LED;            // turn ON LED
    Soft_Delay(10000000);  // delay
    IO0SET=LED;            // turn OFF LED
    T0IR = 0x00;           // Clear the interrupt flag  
}

void Init_PLL (BYTE MP_Mask, BYTE PCLK_Mask)
{
    //set multiplier and divider of the PLL0
    PLL0CFG = MP_Mask;
    //enable PLL0
    PLL0CON = 0x1;
    //provide feed sequence
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;
    //wait until PLL0 is locked
    while (!(PLL0STAT & PLL0_LOCKED))
    {
       ;
    }
    //connect PLL0
    PLL0CON = 0x3;
    //provide feed sequence
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;
    //set peripheral clock
    VPBDIV  = PCLK_Mask;
    return;
}

void Init_Timer(DWORD Prescale_Val, DWORD Match_Val, WORD Match_Config)
{                                                
    T0PR = Prescale_Val;
    T0MR0 = Match_Val;
    T0MCR = Match_Config;    
    return;
}
void Enable_Timer(BYTE Timer_Num)
{
    if (Timer_Num==0)
    {
        T0TCR = 0x01;
    }
    else
    {
        T1TCR = 0x01;
    }
    return;
}

//interupt handler function
__irq void FIQ_Handler (void)
{
    IO0CLR=LED;            // turn ON LED
    Soft_Delay(10000000);  // delay
    IO0SET=LED;            // turn OFF LED
    T0IR = 0x00;           // Clear the interrupt flag  
}

IO0CLR=LED;            // turn ON LED
    Soft_Delay(10000000);  // delay
    IO0SET=LED;            // turn OFF LED

//interupt handler function
__irq void FIQ_Handler (void)
{
    IO0CLR=LED;            // turn ON LED
//    Soft_Delay(10000000);  // delay
//    IO0SET=LED;            // turn OFF LED
//    T0IR = 0x00;           // Clear the interrupt flag  
}

// Pre-defined interrupt handlers that may be directly
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (SWI_Handler?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)

// Exception Vectors
// Mapped to Address 0.
// Absolute addressing mode must be used.

Vectors:        LDR     PC,Reset_Addr        
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                NOP                            /* Reserved Vector */
;               LDR     PC,IRQ_Addr
                LDR     PC,[PC, #-0x0FF0]      /* Vector from VicVectAddr */
                LDR     PC,FIQ_Addr

Reset_Addr:     DD      Reset_Handler
Undef_Addr:     DD      Undef_Handler?A
SWI_Addr:       DD      SWI_Handler?A
PAbt_Addr:      DD      PAbt_Handler?A
DAbt_Addr:      DD      DAbt_Handler?A
                DD      0                      /* Reserved Address */
IRQ_Addr:       DD      IRQ_Handler?A
FIQ_Addr:       DD      FIQ_Handler?A