#define SLOWCLOCK                32768        //* In Hz
#define MAIN_OSC_CLK                        16000000    //* In Hz
#define CPU_HZ                                  (MAIN_OSC_CLK * 45 / 4) // Processor clock (180,000000 MHz for PCK).
#define MASTER_CLOCK                            (CPU_HZ / 3) // Master clock 60.000 MHz

#define  BSP_CLK_DBGU_BAUD_RATE                       115200

#define    PLLAR                           0x202CBF04    // 180,000000 MHz for PCK
#define    PLLBR                           0x10173E04    // 48,000000 MHz (divider by 2 for USB)
#define    MCKR                            0x00000202    // PCK/3 = MCK Master Clock = 60,000000 MHz with PLLA selected


#define C1_IDC        (1<<2)    // icache and/or dcache off/on
#define DRAM_SIZE       0x1000000

#define BASE_EBI_CS1_ADDRESS    0x20000000    //* base address to access memory on CS1

void AT91F_InitSDRAM()
{
        int     i;
    volatile int     *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;
        
        //unsigned int sdram_cfg;

    //* Configure PIOC as peripheral (D16/D31)
    AT91F_SDRC_CfgPIO();
    
    // Setup MEMC to support CS0=FLASH, CS1=SDRAM
    AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A_SDRAMC;
    AT91C_BASE_EBI->EBI_CFGR = (AT91C_EBI_DBPUC & 0x00) | (AT91C_EBI_EBSEN & 0x00);

    //* Init SDRAM
        
        #define AT91C_SDRC_TWR_1        ((unsigned int) 0x1 <<  7) //  10ns (SDRC) Number of Write Recovery Time Cycles
        #define AT91C_SDRC_TRC_6        ((unsigned int) 0x6 << 11) // -70ns (SDRC) Number of RAS Cycle Time Cycles
        #define AT91C_SDRC_TRP_2        ((unsigned int) 0x2 << 15) // -20ns (SDRC) Number of RAS Precharge Time Cycles
        #define AT91C_SDRC_TRCD_2       ((unsigned int) 0x2 << 19) // -20ns (SDRC) Number of RAS to CAS Delay Cycles
        #define AT91C_SDRC_TRAS_4       ((unsigned int) 0x4 << 23) // -50ns (SDRC) Number of RAS Active Time Cycles
        #define AT91C_SDRC_TXSR_1       ((unsigned int) 0x1 << 27) // (SDRC) Number of Command Recovery Time Cycles

        
        #define SDRC_CR_VAL         \
    (             \
     AT91C_SDRC_NR_12    |\
     AT91C_SDRC_NB_4_BANKS    |\
     AT91C_SDRC_CAS_2    |\
     AT91C_SDRC_TWR_1    |\
     AT91C_SDRC_TRC_6    |\
     AT91C_SDRC_TRP_2    |\
     AT91C_SDRC_TRCD_2    |\
     AT91C_SDRC_TRAS_4    |\
     AT91C_SDRC_TXSR_1     \
    )


    //* 1. A minimum pause of 200us is provided to precede any signal toggle
        //sdram_cfg = AT91C_SDRC_NC_9 | SDRC_CR_VAL;
    //AT91C_BASE_SDRC->SDRC_CR = sdram_cfg;
    AT91C_BASE_SDRC->SDRC_CR = AT91C_SDRC_NC_8 | SDRC_CR_VAL;

    //* 2. A Precharge All command is issued to the SDRAM
    AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
    *pSDRAM = 0;

    //* 3. Eight Auto-refresh are provided
    AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
    for(i=0;i<8;i++)
        *pSDRAM = 0;

    //* 4. A mode register cycle is issued to program the SDRAM parameters
    AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
    *(pSDRAM+0x80) = 0;

    //* 5. Write refresh rate into SDRAMC refresh timer COUNT register
        AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT & (64 * (MASTER_CLOCK / 1000) / 4096));
        *pSDRAM = 0;

        // Extra: Self refresh on
        AT91C_BASE_SDRC->SDRC_SRR = AT91C_SDRC_SRCB;
        *pSDRAM = 0;
        
    //* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
    AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NORMAL_CMD;
    *pSDRAM = 0;
}