void timer_init ( void )

{
    
  
      unsigned int mask;  
      mask= TC_CLKS_MCK32 | AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR;
      
      AT91F_TC_Open(AT91C_BASE_TC1,mask,AT91C_ID_TC1);

      AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TC1,   TIMER1_INTERRUPT_LEVEL,AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,tm1_per_irq_handler);
      AT91C_BASE_AIC->AIC_EOICR = 0;
      __enable_interrupt();    
      AT91C_BASE_TC1->TC_IER = AT91C_TC_CPCS; // разр прерыв на уровне TC1 по достижению RC
      AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TC1); // разр прерывания на уровне AIC
    
      AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;    // сброс и запуск TC1      
                              
          
}



void AT91F_TC_Open ( AT91PS_TC TC_pt, unsigned int Mode, unsigned int TimerId)

{
    unsigned int mask;
    
    
    mask = AT91C_PB14_TIOA1 | AT91C_PB15_TIOB1 | AT91C_PB10_TCLK1;
    
    AT91C_BASE_PIOB->PIO_PDR =mask; // запр PIO
    AT91C_BASE_PIOB->PIO_BSR =mask; // подкл к пер B  
  
    AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<< TimerId );
        
    TC_pt->TC_CCR = AT91C_TC_CLKDIS; //* Disable the clock and the interrupts
    TC_pt->TC_IDR = 0xFFFFFFFF;
        
    AT91C_BASE_TC1->TC_RA=0x7FFF; // загр RA
    AT91C_BASE_TC1->TC_RC=0xFFFE; // загр RC

    TC_pt->TC_SR;  //* Clear status bit
    TC_pt->TC_CMR = Mode; //* Set the Mode of the Timer Counter

    TC_pt->TC_CCR = AT91C_TC_CLKEN; //* Enable the clock

}

// Timer outputs
AT91C_BASE_PIOA->PIO_MDDR = (1UL<<16) | (1UL<<15) | (1UL<<1) | (1UL<<0); // push-pull
AT91C_BASE_PIOA->PIO_OER = (1UL<<16) | (1UL<<15) | (1UL<<1) | (1UL<<0); // out
AT91C_BASE_PIOA->PIO_BSR = (1UL<<16) | (1UL<<15) | (1UL<<1) | (1UL<<0); // periph. B
AT91C_BASE_PIOA->PIO_PDR = (1UL<<16) | (1UL<<15) | (1UL<<1) | (1UL<<0); // outputs are peripherial

AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_ADC) | (1<<AT91C_ID_TC0) | (1<<AT91C_ID_TC1);
AT91C_BASE_TCB->TCB_TC0.TC_CCR = AT91C_TC_CLKDIS; // disable TC0 clock
AT91C_BASE_TCB->TCB_TC1.TC_CCR = AT91C_TC_CLKDIS; // disable TC1 clock
AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;

// --- TC0 used to start ADC conversion ---
AT91C_BASE_TCB->TCB_TC0.TC_IDR = AT91C_TC_ETRGS
| AT91C_TC_LDRBS | AT91C_TC_LDRAS \
| AT91C_TC_CPCS | AT91C_TC_CPBS | AT91C_TC_CPAS \
| AT91C_TC_LOVRS | AT91C_TC_COVFS;
AT91C_BASE_TCB->TCB_TC0.TC_CMR =
AT91C_TC_BSWTRG_NONE | AT91C_TC_BEEVT_NONE | AT91C_TC_BCPC_NONE | AT91C_TC_BCPB_NONE // TIOB: none
| AT91C_TC_ASWTRG_NONE | AT91C_TC_AEEVT_NONE | AT91C_TC_ACPC_SET | AT91C_TC_ACPA_CLEAR // TIOA: set on RC, clear on RA
| AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO // waveform mode, up to RC
| AT91C_TC_ENETRG | AT91C_TC_EEVT_XC2 | AT91C_TC_EEVTEDG_NONE // no ext. trigger
| (0 * AT91C_TC_CPCDIS) | (0 * AT91C_TC_CPCSTOP) | AT91C_TC_BURST_NONE | (0 * AT91C_TC_CLKI) | AT91C_TC_CLKS_TIMER_DIV1_CLOCK;

AT91C_BASE_TCB->TCB_TC0.TC_RC = (MCK / 2) / ADC_SAMPLE_RATE - 1; // TC0CLK = MCLK/2
AT91C_BASE_TCB->TCB_TC0.TC_RA = (MCK / 2) / ADC_SAMPLE_RATE / 2 - 1;
AT91C_BASE_TCB->TCB_TC0.TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; // reset and enable TC0 clock