B           InitReset         ; 0x00 Reset handler
undefvec:
                B           undefvec          ; 0x04 Undefined Instruction
swivec:
                B           swivec            ; 0x08 Software Interrupt
pabtvec:
                B           pabtvec        ; 0x0C Prefetch Abort
dabtvec:
                B           dabtvec        ; 0x10 Data Abort
rsvdvec:
                B           rsvdvec        ; 0x14 reserved
irqvec:
                B           IRQ_Handler_Entry ; 0x18 IRQ
fiqvec:                       ; 0x1c FIQ


void AT91F_LowLevelInit( void)
{
unsigned int i;
  AT91C_BASE_RSTC->RSTC_RMR = 0xa5000801;
  AT91PS_PMC     pPMC = AT91C_BASE_PMC;
  //* Set Flash Waite sate
  //  Single Cycle Access at Up to 30 MHz, or 40
  //  if MCK = 47923200 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
  AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(48 <<16)) | AT91C_MC_FWS_1FWS;
  //* Set MCK at 47 923 200
  // 1 Enabling the Main Oscillator:
  // SCK = 1/32768 = 30.51 uSecond
  // Start up time = 8 * 6 / SCK = 48 * 30.51 = 1,46484375 ms
  pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
  // Wait the startup time
  while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
  // 2 Checking the Main Oscillator Frequency (Optional)
  // 3 Setting PLL and divider:
  // - div by 5 Fin = 3,6864 =(18,432 / 5)
  // - Mul 25+1: Fout =    95,8464 =(3,6864 *26)
  // for 96 MHz the erroe is 0.16%
  // Field out NOT USED = 0
  // PLLCOUNT pll startup time estimate at : 0.844 ms
  // PLLCOUNT 28 = 0.000844 /(1/32768)
  pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
                    (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                    (AT91C_CKGR_MUL & (25<<16)));
  // Wait the startup time
  while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
  while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  // 4. Selection of Master Clock and Processor Clock
  // select the PLL clock divided by 2
  pPMC->PMC_MCKR =  AT91C_PMC_PRES_CLK_2;
  while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
  while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
  // Set up the default interrupts handler vectors
  AT91C_BASE_AIC->AIC_EOICR = 0xFFFFFFFF;
  AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
  AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
  for(i=0;i<31;i++)
  {
    AT91C_BASE_AIC->AIC_SMR[i] = 0;
  }
  AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;
  for (i=1;i < 31; i++)
  {
    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;
  }
  AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler;
}

void init_inquiry_timer()
{
  AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,1<<INQUIRYTIMERID);
  AT91F_TC_Open(INQUIRYTIMERREG,TC_CLKS_MCK1024|AT91C_TC_WAVESEL_UP_AUTO,INQUIRYTIMERID);
  AT91F_AIC_ConfigureIt(AT91C_BASE_AIC,INQUIRYTIMERID,INQUIRYINTPRIOR,AT91C_AIC_SRCTYPE_INT_LEVEL_SE
NSITIVE, _one_sec_timer_isr);
  AT91F_AIC_EnableIt(AT91C_BASE_AIC,INQUIRYTIMERID);
  INQUIRYTIMERREG->TC_IER = AT91C_TC_CPCS;
  INQUIRYTIMERREG->TC_RC = 46800;
  INQUIRYTIMERREG->TC_CCR = AT91C_TC_SWTRG;
}

#ifdef   AIC_PROTECT_MODE
   bAIC->AIC_DCR = AT91C_AIC_DCR_PROT;    // set protected mode
#else
   bAIC->AIC_DCR = 0;
#endif

#ifdef   AIC_PROTECT_MODE
   bAIC->AIC_IVR = 0;               // for protected mode of AIC
#endif