entity WEST_XC3S500E is
    port (
        SYS_BUS_DIFF1_N<0> : inout std_logic;
        SYS_BUS_DIFF1_N<10> : inout std_logic;
        SYS_BUS_DIFF1_N<11> : inout std_logic;
        SYS_BUS_DIFF1_N<12> : inout std_logic;
        SYS_BUS_DIFF1_N<13> : inout std_logic;
        SYS_BUS_DIFF1_N<14> : inout std_logic;
        SYS_BUS_DIFF1_N<15> : inout std_logic;
        SYS_BUS_DIFF1_N<1> : inout std_logic;
        SYS_BUS_DIFF1_N<2> : inout std_logic;
        SYS_BUS_DIFF1_N<3> : inout std_logic;
        SYS_BUS_DIFF1_N<4> : inout std_logic;
        SYS_BUS_DIFF1_N<5> : inout std_logic;
        SYS_BUS_DIFF1_N<6> : inout std_logic;
        SYS_BUS_DIFF1_N<7> : inout std_logic;
        SYS_BUS_DIFF1_N<8> : inout std_logic;
        SYS_BUS_DIFF1_N<9> : inout std_logic;
        COM_RX : in std_logic;
        COM_TX : out std_logic;
        SELF_CLK : in std_logic;
        SELF_DIN : in std_logic;
        SELF_DOUT : out std_logic;
        SELF_HSWAP : in std_logic;
        SELF_INIT_B : out std_logic;
        SELF_M : in std_logic_vector (0 to 2);
        SRAM_CE2 : inout std_logic;
        SRAM_CLK : inout std_logic;
        SRAM_DATA : inout std_logic_vector (0 to 31);
        SRAM_DATA_P : inout std_logic_vector (0 to 3);
        SRAM_NADV : inout std_logic;
        SRAM_NBW : inout std_logic_vector (1 to 4);
        SRAM_NCE1 : inout std_logic;
        SRAM_NCE2 : inout std_logic;
        SRAM_NCEN : inout std_logic;
        SRAM_NDE : inout std_logic;
        SRAM_NLBD : inout std_logic;
        SRAM_NRW : inout std_logic;
        SRAM_ZZ : inout std_logic;
        SW : in std_logic_vector (0 to 2);
        G0_CLK : in std_logic;
        SRAM_ADR : in std_logic_vector (0 to 16);
        SYS_BUS_DIFF1_P : inout std_logic_vector (0 to 15)    );
end WEST_XC3S500E;