static void prvSetupTimerInterrupt( void )
{
AT91PS_PITC pxPIT = AT91C_BASE_PITC;

        extern void ( vPortPreemptiveTick )( void );
    AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );

    pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;

    AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
}

vPortPreemptiveTick
    portSAVE_CONTEXT        ; Save the context of the current task.

    LDR R0, =vTaskIncrementTick; Increment the tick count - this may wake a task.
    mov lr, pc
    BX R0
    LDR R0, =vTaskSwitchContext; Select the next task to execute.
    mov lr, pc
    BX R0

    LDR    R14, =AT91C_BASE_PITC; Clear the PIT interrupt
    LDR    R0, [R14, #PITC_PIVR ]

    LDR R14, =AT91C_BASE_AIC; Mark the End of Interrupt on the AIC
    STR    R14, [R14, #AIC_EOICR]

    portRESTORE_CONTEXT        ; Restore the context of the selected task.

static void vHW( void *pvParameters )
{
    ( void ) pvParameters;

    for(;; )
    {
        var++;
    }
}

int main (void)
{
    xTaskCreate(vHW, "Hi", 512, NULL, tskIDLE_PRIORITY + 1, NULL );
    vTaskStartScheduler();
}

portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
portSTACK_TYPE *pxOriginalTOS;

    pxOriginalTOS = pxTopOfStack;

    /* Setup the initial stack of the task.  The stack is set exactly as
    expected by the portRESTORE_CONTEXT() macro. */

    /* First on the stack is the return address - which in this case is the
    start of the task.  The offset is added to make the return address appear
    as it would within an IRQ ISR. */
    *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;        
    pxTopOfStack--;

    *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;    /* R14 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
    pxTopOfStack--;
    *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212;    /* R12 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;    /* R11 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010;    /* R10 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909;    /* R9 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808;    /* R8 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707;    /* R7 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606;    /* R6 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505;    /* R5 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404;    /* R4 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303;    /* R3 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202;    /* R2 */
    pxTopOfStack--;    
    *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101;    /* R1 */
    pxTopOfStack--;    

    /* When the task starts is will expect to find the function parameter in
    R0. */
    *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
    pxTopOfStack--;


    *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;


    *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;

    return pxTopOfStack;
}

    LDR        R1, =pxCurrentTCB
    LDR        R0, [R1]
    LDR        LR, [R0]

; The critical nesting depth is the first item on the stack.     
; Load it into the ulCriticalNesting variable.                     
    LDR        R0, =ulCriticalNesting
    LDMFD    LR!, {R1}
    STR        R1, [R0]

; Get the SPSR from the stack.                                     
    LDMFD    LR!, {R0}
    MSR        SPSR_cxsf, R0

; Restore all system mode registers for the task.                 
    LDMFD    LR, {R0-R14}^
    NOP

; Restore the return address.                                     
    LDR        LR, [LR, #+60]

; And return - correcting the offset in the LR to obtain the     
; correct address.                                                 
    SUBS    PC, LR, #4