/* identify the Entry Point (_vec_reset is defined in file crt.s) */
ENTRY(_vec_reset)

/* specify the AT91SAM7S64 memory areas */
MEMORY
{
flash : ORIGIN = 0, LENGTH = 64K /* FLASH EPROM */
ram : ORIGIN = 0x00200000, LENGTH = 16K /* static RAM area */
}


/* define a global symbol _stack_end (see analysis in annotation above) */
_stack_end = 0x203FFC;

/* now define the output sections */
SECTIONS
{
. = 0; /* set location counter to address zero */

.text : /* collect all sections that should go into FLASH after startup */
{
*(.text) /* all .text sections (code) */
*(.rodata) /* all .rodata sections (constants, strings, etc.) */
*(.rodata*) /* all .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* all .glue_7 sections (no idea what these are) */
*(.glue_7t) /* all .glue_7t sections (no idea what these are) */
_etext = .; /* define a global symbol _etext just after the last code byte */
} >flash /* put all the above into FLASH */

.data : /* collect all initialized .data sections that go into RAM */
{
_data = .; /* create a global symbol marking the start of the .data section */
*(.data) /* all .data sections */
_edata = .; /* define a global symbol marking the end of the .data section */
} >ram AT >flash /* put all the above into RAM (but load the LMA initializer copy into FLASH) */

.bss : /* collect all uninitialized .bss sections that go into RAM */
{
_bss_start = .; /* define a global symbol marking the start of the .bss section */
*(.bss) /* all .bss sections */
} >ram /* put all the above in RAM (it will be cleared in the startup code */

. = ALIGN(4); /* advance location counter to the next 32-bit boundary */
_bss_end = .; /* define a global symbol marking the end of the .bss section */
}
_end = .; /* define a global symbol marking the end of application RAM */

                
         ORG 0x18
         ldr     pc,[pc,#-0xFF0]; Jump directly to the address given by the AIC

   ldr    pc, RESET_ADDR
    ldr    pc, UNDEF_ADDR
    ldr    pc, SWI_ADDR
    ldr    pc, PREFETCH_ABORT_ADDR
    ldr    pc, DATA_ABORT_ADDR
    .word    0
    ldr     pc,[pc,#-0xF20]; IRQ
    ldr     pc,[pc,#-0xF20]; FIQ
RESET_ADDR:        .word    RESET_handler
UNDEF_ADDR:        .word    UNDEF_handler
SWI_ADDR:        .word    SWI_handler
PREFETCH_ABORT_ADDR:    .word    PREFETCH_ABORT_handler
DATA_ABORT_ADDR:    .word    DATA_ABORT_handler

0xFFFFF100    AIC_IVR
0xFFFFF104   AIC_FVR                                                                                


                 .global _start
                     _start:


0x1000000    ldr     pc,  lab1
0x1000004    ldr     pc,  lab2
0x1000008    ldr     pc,  lab3
0x100000C    ldr     pc, lab4
0x1000010    ldr     pc,  lab5
0x1000014   .word    0
0x1000018    ldr     pc,[pc,#-0xF20];               @IRQ_ADDR
0x100001C    ldr     pc,[pc,#-0xF20];               @  FIQ_ADDR    

lab1:
....
lab2:
....