DDRB = ((1<<MOSI)|(1<<SCLK)|(1<<SS));

//Enable SPI, Select Master, SCLK idles high,
//Sample on rising edge Setup on falling edge,
//SCLK=F_CPU/4
SPCR =0x52; //((1<<SPE)|(1<<MSTR)|(1<<CPOL)|(1<<CPHA));

//Serially reset the Chip
SPDR = 0xFF;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Serially reset the Chip
SPDR = 0xFF;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Serially reset the Chip
SPDR = 0xFF;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Serially reset the Chip
SPDR = 0xFF;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Serially reset the Chip
SPDR = 0xFF;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));


//Send to Comm Reg: Next Write Clk
SPDR = 0b00100000; //0x20

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Send to ClkReg: Clock Bits and Update rate
SPDR = 0x18; //0b00011000;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Send to Comm Reg: write setup
SPDR = 0b00010000; //0x10

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

//Send to Setup: FSYNC, Gain, Conditions, Self Calibration
SPDR = 0b01000100;

//Wait for transfer
while(!(SPSR & (1<<SPIF)));

while(1)
{
//Is DDRY pin low/data ready?

//Send to Comm: next read Data
SPDR = 0b00111000; // 0x38

//Wait for transfer
while(!(SPSR & (1<<SPIF)));
DDRB=0x10;
DDRB.5=1;
CLK=1;
while(DRDY);
delay_us(us1);
CLK=0; delay_us(us1);
while(i<16)
{
CLK=1;delay_us(us1);
adc_rez[i]='0';
if(D_OUT==1) adc_rez[i]='1';
CLK=0;delay_us(us1);
i++;
}