ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFS
   component:
       PAD symbol "clk_out_n" (Pad Signal = clk_out_n)
       SlaveBuffer symbol "U2/SLAVEBUF.DIFFOUT" (Output Signal = clk_out_n)
   Each of the following constraints specifies an illegal physical site for a
   component of type DIFFS:
       Symbol "clk_out_n" (LOC=AB13)
   Please correct the constraints accordingly.

-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;


-- other libraries declarations
-- synopsys translate_off
library VIRTEX2;
library IEEE;
use IEEE.vital_timing.all;
-- synopsys translate_on

entity top is
  port(
       CLK_in : in std_ulogic;
       clk_out_n : out std_ulogic;
       clk_out_p : out std_ulogic
  );
end top;

architecture top of top is

---- Component declarations -----

component OBUFDS
-- synopsys translate_off
  generic(
       CAPACITANCE : STRING := "DONT_CARE";
       DRIVE : INTEGER := 12;
       IOSTANDARD : STRING := "DEFAULT";
       SLEW : STRING := "SLOW"
  );
-- synopsys translate_on
  port (
       I : in std_ulogic;
       O : out std_ulogic;
       OB : out std_ulogic
  );
end component;

---- Configuration specifications for declared components

-- synopsys translate_off
for U2 : OBUFDS use entity virtex2.OBUFDS;
-- synopsys translate_on

begin

----  Component instantiations  ----

U2 : OBUFDS
  port map(
       I => CLK_in,
       O => clk_out_p,
       OB => clk_out_n
  );


end top;

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "CLK_in"  LOC = "aa13";
NET "clk_out_p"  LOC = "ab12" | IOSTANDARD = LVDS_33  | SLEW = FAST;
NET "clk_out_n"  LOC = "ab13" | IOSTANDARD = LVDS_33  | SLEW = FAST;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE