C:\openocd\src>openocd -f WigglerF.cfg
Open On-Chip Debugger 0.1.0 (2009-02-02-20:43) Release


BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS


$URL: https://kc8apf@svn.berlios.de/svnroot/repos...enocd-0.1.0/src
/openocd.c $
jtag_speed: 0
OLD SYNTAX: DEPRECATED - translating to new syntax
jtag newtap CHIP TAP -irlen 4 -ircapture 0x1 -irvalue 0xf
Example: STM32 has 2 taps, the cortexM3(len4) + boundryscan(len5)
jtag newtap stm32 cortexm3 ....., thus creating the tap: "stm32.cortexm3"
jtag newtap stm32 boundry ....., and the tap: "stm32.boundery"
And then refer to the taps by the dotted name.
NEW COMMAND:
invalid command name "daemon_startup_reset"

C:\openocd\src>

telnet_port 4444
gdb_port 3333
interface parport
parport_port 0xDD00
parport_cable wiggler
jtag_speed 0
reset_config srst_only srst_pulls_trst
jtag_device 4 0x1 0xf 0xe
daemon_startup reset
target arm7tdmi little run_and_init 0 arm7tdmi
run_and_halt_time 0 30
target_script 0 reset openocd_at91sam7x_flash.script
working_area 0 0x00200000 0x4000 nobackup
flash bank at91sam7 0 0 0 0 0

source [find parport.cfg]
source [find stm32.cfg]

source [find C:\\openocd\\src\\target\\interface\\parport.cfg]  
source [find C:\\openocd\\src\\target\\target\\sam7se512.cfg]

C:\openocd\src>openocd -f config.cfg
Open On-Chip Debugger 0.1.0 (2009-02-02-20:43) Release
BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS
$URL: https://kc8apf@svn.berlios.de/svnroot/repos/openocd/tags/openocd-0.1.0/src/openocd.c $
jtag_speed: 0
Error: missing privileges for direct i/o
Runtime error, file "command.c", line 456:

C:\openocd\src>

int command_run_line(command_context_t *context, char *line)
{
/* all the parent commands have been registered with the interpreter
* so, can just evaluate the line as a script and check for
* results
*/
/* run the line thru a script engine */
int retval=ERROR_FAIL;
int retcode;
/* Beware! This code needs to be reentrant. It is also possible
* for OpenOCD commands to be invoked directly from Tcl. This would
* happen when the Jim Tcl interpreter is provided by eCos for
* instance.
*/
Jim_DeleteAssocData(interp, "context");
retcode = Jim_SetAssocData(interp, "context", NULL, context);
if (retcode == JIM_OK)
{
/* associated the return value */
Jim_DeleteAssocData(interp, "retval");
retcode = Jim_SetAssocData(interp, "retval", NULL, &retval);
if (retcode == JIM_OK)
{
retcode = Jim_Eval_Named(interp, line, __THIS__FILE__, __LINE__ ); // Вот это 456 строка, при запуске, сообщает что здесь ошибка

Jim_DeleteAssocData(interp, "retval");
}
Jim_DeleteAssocData(interp, "context");
}
if (retcode == JIM_ERR) {
if (retval!=ERROR_COMMAND_CLOSE_CONNECTION)
{
/* We do not print the connection closed error message */
Jim_PrintErrorMessage(interp);
}
if (retval==ERROR_OK)
{
/* It wasn't a low level OpenOCD command that failed */
return ERROR_FAIL;
}
return retval;
} else if (retcode == JIM_EXIT) {
/* ignore. */
/* exit(Jim_GetExitCode(interp)); */
} else {
const char *result;
int reslen;

result = Jim_GetString(Jim_GetResult(interp), &reslen);
int i;
char buff[256+1];
for (i = 0; i < reslen; i += 256)
{
int chunk;
chunk = reslen - i;
if (chunk > 256)
chunk = 256;
strncpy(buff, result+i, chunk);
buff[chunk] = 0;
LOG_USER_N("%s", buff);
}
LOG_USER_N("%s", "\n");
retval=ERROR_OK;
}
return retval;
}

C:\openocd\src>openocd -f config.cfg
Open On-Chip Debugger 0.1.0 (2009-02-03-17:29) Release
BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS

$URL: https://kc8apf@svn.berlios.de/svnroot/repos...0/src/openocd.c $
jtag_speed: 0
Info : JTAG tap: sam7se512.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787
, Part: 0xf0f0, Version: 0x3)
Error: JTAG tap: sam7se512.cpu got: 0x3f0f0f0f (mfg: 0x787, part: 0x
f0f0, ver: 0x3)
Error: JTAG tap: sam7se512.cpu expected 1 of 1: 0xffffffff (mfg: 0x7ff, part: 0x
ffff, ver: 0xf)
Error: trying to validate configured JTAG chain anyway...
Warn : no tcl port specified, using default port 6666

jtag_speed: 0
Info : JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
Info : JTAG Tap/device matched
Error: couldn't bind to socket: Address already in use

Open On-Chip Debugger (2008-06-19 19:00) svn: 717
URL: http://svn.berlios.de/svnroot/repos/openocd/trunk
Info: options.c:50 configuration_output_handler(): jtag_speed: 3, 3
Info: options.c:50 configuration_output_handler(): Open On-Chip Debugger (2008-06-19 19:00) svn: 717
Info: jtag.c:1389 jtag_examine_chain(): JTAG device found: 0x4f1f0f0f (Manufacturer: 0x787, Part: 0xf1f0, Version: 0x4)
Warning: embeddedice.c:185 embeddedice_build_reg_cache(): EmbeddedICE version 7 detected, EmbeddedICE handling might be broken
Info: jtag.c:1389 jtag_examine_chain(): JTAG device found: 0x4f1f0f0f (Manufacturer: 0x787, Part: 0xf1f0, Version: 0x4)
User: target.c:436 target_process_reset(): Timed out waiting for halt after reset
Info: server.c:78 add_connection(): accepting 'gdb' connection from 0
Warning: gdb_server.c:416 gdb_get_packet_inner(): acknowledgment received, but no packet pending
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Info: server.c:395 server_loop(): dropped 'gdb' connection
Info: server.c:78 add_connection(): accepting 'gdb' connection from 0
Warning: gdb_server.c:416 gdb_get_packet_inner(): acknowledgment received, but no packet pending
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted
Warning: arm7_9_common.c:1829 arm7_9_read_memory(): target not halted

#daemon configuration
telnet_port 4444
gdb_port 3333

# tell gdb our flash memory map
# and enable flash programming
gdb_memory_map enable
gdb_flash_program enable

#interface
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
jtag_speed 3
jtag_nsrst_delay 200 # <- заработало после добавления вот этого
jtag_ntrst_delay 200 # <-

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst

#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

#target configuration
daemon_startup reset

#target <type> <startup mode>
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4

run_and_halt_time 0 30

working_area 0 0x40000000 0x4000 nobackup

#flash configuration
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum

# For more information about the configuration files, take a look at:
# http://openfacts.berlios.de/index-en.phtml...n-Chip+Debugger

ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F

I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */

/*
* Register Base Address
*/
AIC_BASE = 0xFFFFF000
AIC_EOICR_OFF = 0x130
AIC_IDCR_OFF = 0x124

RSTC_MR = 0xFFFFFD08
RSTC_KEY = 0xA5000000
RSTC_URSTEN = 0x00000001

WDT_BASE = 0xFFFFFD40
WDT_MR_OFF = 0x00000004
WDT_WDDIS = 0x00008000

MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100

@--------------------------------------------------------
@ PMC адреса регистров
PMC_BASE = 0xFFFFFC00
PMC_SCER = 0x00
PMC_SCDR = 0x04
PMC_MOR = 0x20
PMC_MCFR = 0x24
PMC_PLLR = 0x2C
PMC_MCKR = 0x30
PMC_SR = 0x68
PMC_PCK0 = 0x40
@ PMC биты
PMC_MOSCEN = (1 << 0) @ разрешение тактового генератора
PMC_OSCBYPASS = (1 << 1) @ включение тактового генератора
PMC_OSCOUNT = (0xFF << 8) @ время запуска основного тактового генератора.
@ PLL биты
PMC_DIV = (0x01 << 0) @ предварительный делитель
PMC_PLLCOUNT = (0x3F << 8) @ Определяет число тактов сигнала SLCK, через которое устанавливается LOCK
PMC_OUT = (0x00 << 14) @ Диапазон тактовых частот ФАПЧ
PMC_MUL = (0x07 << 16) @ множитель ФАПЧ коэффициент (MUL+1)
PMC_USBDIV = (0x01 << 28) @ предварительный делитель USB 28 / 2 ; 29 / 4
@ MCKR биты
PMC_CSS = (3 << 0) @ Выбор источника основного синхронизирующего сигна 3pll
PMC_PRES = (0 << 2) @ Предделитель основного генератора
@ SR биты
PMC_MOSCS = (1 << 0) @ Тактовый генератор стабилизирован
PMC_LOCK = (1 << 2) @ ФАПЧ зафиксирована
PMC_MCKRDY = (1 << 3) @ Состояние главного синхронизирующего сигнала MCK
PMC_PCKRDY0 = (1 << 8) @ Состояние программируемого тактового сигнала
@ Регистры
PMC_MOR_Val = (PMC_OSCOUNT | PMC_MOSCEN)
PMC_PLLR_Val = (PMC_USBDIV | PMC_MUL | PMC_OUT | PMC_PLLCOUNT | PMC_DIV)
PMC_MCKR_Val = (PMC_PRES | PMC_CSS)
@--------------------------------------------------------

.section .vectors,"ax"
.code 32

/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
_vectors:
ldr pc, ResetAddr /* Reset */
ldr pc, UndefAddr /* Undefined instruction */
ldr pc, SWIAddr /* Software interrupt */
ldr pc, PAbortAddr /* Prefetch abort */
ldr pc, DAbortAddr /* Data abort */
ldr pc, ReservedAddr /* Reserved */
ldr pc, IRQAddr /* IRQ interrupt */
ldr pc, FIQAddr /* FIQ interrupt */


ResetAddr: .word ResetHandler
UndefAddr: .word UndefHandler
SWIAddr: .word SWIHandler
PAbortAddr: .word PAbortHandler
DAbortAddr: .word DAbortHandler
ReservedAddr: .word 0
IRQAddr: .word IRQHandler
FIQAddr: .word FIQHandler

.ltorg

.section .init, "ax"
.code 32

.global ResetHandler
.global ExitFunction
.extern main
/****************************************************************************/
/* Reset handler */
/****************************************************************************/
ResetHandler:
@----------------------------------------------------------------------------------------
@ включение тактового генератора и установка времени запуска
ldr r0, = PMC_BASE
ldr r1, = PMC_MOR_Val
str r1, [r0, #PMC_MOR]
@ настройка PMC_USBDIV PMC_MUL PMC_OUT PMC_PLLCOUNT PMC_DIV
ldr r1, = PMC_PLLR_Val
str r1, [r0, #PMC_PLLR]
@ выбор источника генератора и настройка предварительного делителя
ldr r1, = PMC_MCKR_Val
str r1, [r0, #PMC_MCKR]
@----------------------------------------------------------------------------------------
/*
* The watchdog is enabled after processor reset. Disable it.
*/
ldr r1, =WDT_BASE
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]


/*
* сброс
*/
ldr r0, = (RSTC_KEY | RSTC_URSTEN )
ldr r1, = RSTC_MR
str r0, [r1, #0]


/*
* Use 2 cycles for flash access.
*/
ldr r1, =MC_BASE
ldr r0, =MC_FWS_1FWS
str r0, [r1, #MC_FMR_OFF]


/*
* Disable all interrupts. Useful for debugging w/o target reset.
*/
ldr r1, =AIC_BASE
mvn r0, #0
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]

/*
* Setup a stack for each mode
*/
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end

msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end

msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end

msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end

msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end


/*
* Clear .bss section
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
ldr r3, =0
bss_clear_loop:
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop


/*
* Jump to main
*/
@ mrs r0, cpsr
@ bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
@ msr cpsr, r0


mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, = main
mov lr, pc
bx r2 /* And jump... */

ExitFunction:
nop
nop
nop
b ExitFunction


/****************************************************************************/
/* Default interrupt handler */
/****************************************************************************/

UndefHandler:
b UndefHandler

SWIHandler:
b SWIHandler

PAbortHandler:
b PAbortHandler

DAbortHandler:
b DAbortHandler

IRQHandler:
b IRQHandler

FIQHandler:
b FIQHandler

.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler

.ltorg