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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SDRAM_MODULE is
Port ( CLK_SDRAM_IN : in STD_LOGIC;
CLK_SDRAM_OUT : out STD_LOGIC:='0';
CKE_OUT : out STD_LOGIC:='0';
WE_OUT : out STD_LOGIC:='0';
RAS_OUT : out STD_LOGIC:='0';
CAS_OUT : out STD_LOGIC:='0';
DQM_OUT : out STD_LOGIC_VECTOR (1 downto 0):=b"11";
BA_OUT : out STD_LOGIC_VECTOR (1 downto 0):=b"00";
LED : out STD_LOGIC:='0';
ADDRES_OUT : out STD_LOGIC_VECTOR (11 downto 0):="ZZZZZZZZZZZZ";
DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DATA_T : out STD_LOGIC_VECTOR (15 downto 0):=b"1111111111111111"
);

end SDRAM_MODULE;

architecture Behavioral of SDRAM_MODULE is

begin
process (CLK_SDRAM_IN)

variable n : integer range 0 to 3000;

begin
if CLK_SDRAM_IN'event and CLK_SDRAM_IN='1' then

case n is
when 0 => CKE_OUT <= '1'; RAS_OUT <= '1'; CAS_OUT <= '1'; WE_OUT <= '1'; n:=n+1;--устанавливаем команду "NOP" и ждем >200 мкс

when 2500 => RAS_OUT <= '0'; CAS_OUT <= '1'; WE_OUT <= '0'; ADDRES_OUT <= "010000000000"; n:=n+1;-- "PRECHARGE" all banks + пауза 3 такта (>=20ns)
when 2503 => RAS_OUT <= '0'; CAS_OUT <= '0'; WE_OUT <= '1'; n:=n+1;-- "AUTO REFRESH" + пауза 9 тактов (>=65ns)
when 2512 => RAS_OUT <= '0'; CAS_OUT <= '0'; WE_OUT <= '1'; n:=n+1;-- "AUTO REFRESH" + пауза 9 тактов (>=65ns)
when 2521 => RAS_OUT <= '0'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "001000100011"; n:=n+1;-- "MODE REGISTER SET" + пауза 2 такта
when 2523 => RAS_OUT <= '0'; CAS_OUT <= '1'; WE_OUT <= '1'; BA_OUT <= "00"; DQM_OUT <= "00"; ADDRES_OUT <= "000000000000";n:=n+1;--активируем ряд



when 2537 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000000"; DATA_OUT <= b"0000000000000001"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2538 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000001"; DATA_OUT <= b"0000000000000010"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2539 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000010"; DATA_OUT <= b"0000000000000011"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2540 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000011"; DATA_OUT <= b"0000000000000100"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2541 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000100"; DATA_OUT <= b"0000000000000101"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2542 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000101"; DATA_OUT <= b"0000000000000110"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2543 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000110"; DATA_OUT <= b"1010101010101010"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2544 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '0'; BA_OUT <= "00"; ADDRES_OUT <= "000000000111"; DATA_OUT <= b"0101010101010101"; DATA_T <= b"0000000000000000"; n:=n+1;--команда "WRITE"
when 2545 => RAS_OUT <= '1'; CAS_OUT <= '1'; WE_OUT <= '1'; n:=n+1; DATA_T <= b"1111111111111111";--устанавливаем команду "NOP"



when 2566 => RAS_OUT <= '1'; CAS_OUT <= '0'; WE_OUT <= '1'; BA_OUT <= "00"; ADDRES_OUT <= "010000000000"; n:=n+1;--команда "READ"
when 2568 => if DATA_IN = b"0000000000000001" then LED <= '1'; end if; n:=n+1; -- читаем 8 слов




when others => n:=n+1; RAS_OUT <= '1'; CAS_OUT <= '1'; WE_OUT <= '1'; --устанавливаем команду "NOP"
end case;

end if;

CLK_SDRAM_OUT <= CLK_SDRAM_IN;

end process;

end Behavioral;