#include "common/target.h"
#include "common/target.c"

#include "uart_lpc2468.h"
#include "uart_lpc2468.c"

void main(void)
{
//power on target init
TargetResetInit();

//uart0 initialization
uart0_lpc2468_init(9600);


for(;;)
{
//putchar(getchar());
//continue;
/* Loop forever */
if ( UART0Count != 0 )
{
U0IER = IER_THRE | IER_RLS; /* Disable RBR */
UARTSend( (BYTE *)UART0Buffer, UART0Count );
UART0Count = 0;
U0IER = IER_THRE | IER_RLS | IER_RBR; /* Re-enable RBR */
};
}
}

/**************************************************/
//uart0 initialization
WORD uart0_lpc2468_init(DWORD baudrate)
{
DWORD Fdiv;

//set PCUART0 - UART0 power/clock control bit.
PCONP |=(1<<PCUART0);

//set PCLK_UART0=0x01 (PCLK_UART0 = CCLK) - Peripheral clock selection for UART0.
PCLKSEL0 |= PCLK_UART0;

//UART pins and pin modes
PINSEL0 = RXPinON|TXPinON;
PINMODE0 = RXPinPullUP|TXPinPullUP;

//UART0 Line Control Register U0LCR
U0LCR = WordLenth8|StopBit1|ParityDis|BreakDis|DLABEna;

//UART0 baudrate
Fdiv = ( Fpclk / 16 ) / baudrate ; /*baud rate */
U0DLM = Fdiv / 256;
U0DLL = Fdiv % 256;
U0LCR = WordLenth8|StopBit1|ParityDis|BreakDis|DLABDis;

//UARTn FIFO Control Register U0FCR
U0FCR = FIFOEna|RXFIFORes|TXFIFORes|TriggerLevel0;

//install uart0 irq
if ( install_irq( UART0_INT, (void *)UART0Handler, HIGHEST_PRIORITY ) == FALSE )
{
return (FALSE);
}

U0IER = RBR_IE | THRE_IE | IER_RLS; /* Enable UART0 interrupt */

return TRUE;
}
/**************************************************/

DWORD install_irq( DWORD IntNumber, void *HandlerAddr, DWORD Priority )
{
DWORD *vect_addr;
DWORD *vect_cntl;

VICINTENCLEAR = 1 << IntNumber; /* Disable Interrupt */
if ( IntNumber >= VIC_SIZE )
{
return ( FALSE );
}
else
{
/* find first un-assigned VIC address for the handler */
vect_addr = (DWORD *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + IntNumber*4);
vect_cntl = (DWORD *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + IntNumber*4);
*vect_addr = (DWORD)HandlerAddr; /* set interrupt vector */
*vect_cntl = Priority;
VICINTENABLE = 1 << IntNumber; /* Enable Interrupt */
return( TRUE );
}
}

__irq __arm void UART0Handler(void)
{
BYTE IIRValue, LSRValue;
volatile BYTE Dummy;

//__enable_interrupt(); /* handles nested interrupt */

IIRValue = U0IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
{
LSRValue = U0LSR;
/* Receive Line Status */
if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UART0Status = LSRValue;
Dummy = U0RBR; /* Dummy read on RX to clear interrupt, then bail out */
VICADDRESS = 0; /* Acknowledge Interrupt */
return;
}
if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
//Dummy = U0RBR;
UART0Buffer[UART0Count] = U0RBR;
UART0Count++;
if ( UART0Count == BUFSIZE )
{
UART0Count = 0; /* buffer overflow */
}
}
}
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
{
/* Receive Data Available */
UART0Buffer[UART0Count] = U0RBR;
UART0Count++;
if ( UART0Count == BUFSIZE )
{
UART0Count = 0; /* buffer overflow */
}
}
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
{
/* Character Time-out indicator */
UART0Status |= 0x100; /* Bit 9 as the CTI error */
}
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = U0LSR; /* Check status in the LSR to see if valid data in U0THR or not */
if ( LSRValue & LSR_THRE )
{
UART0TxEmpty = 1;
}
else
{
UART0TxEmpty = 0;
}
}

VICADDRESS = 0; /* Acknowledge Interrupt */
return;
}
/**************************************************/