void EINT1_Handler (void) __irq
{
    EXTINT = EINT1;        /* clear interrupt */
        
    IENABLE;            /* handles nested interrupt */
    eint1_counter++;
    if ( eint1_counter & 0x01 )    /* alternate the LED display */
    {
    IOSET1 = 0x000F0000;    /* turn off P1.20~23 */    
    IOCLR1 = 0x00F00000;    /* turn on P1.16~19 */
    }
    else
    {
    IOSET1 = 0x00F00000;    /* turn on P1.20~23 */    
    IOCLR1 = 0x000F0000;    /* turn off P1.16~19 */
    }
    IDISABLE;
    VICVectAddr = 0;        /* Acknowledge Interrupt */
}

// Macros for Interrupt Nesting
#define IENABLE                             /* Nested Interrupts Entry */   \
  __asm { MRS     LR, SPSR      }           /* Copy SPSR_irq to LR     */   \
  __asm { STMFD   SP!, {LR}     }           /* Save SPSR_irq           */   \
  __asm { MSR     CPSR_c, #0x1F }           /* Enable IRQ (Sys Mode)   */   \
  __asm { STMFD   SP!, {LR}     }           /* Save LR                 */   \

#define IDISABLE                            /* Nested Interrupts Exit  */   \
  __asm { LDMFD   SP!, {LR}     }           /* Restore LR              */   \
  __asm { MSR     CPSR_c, #0x92 }           /* Disable IRQ (IRQ Mode)  */   \
  __asm { LDMFD   SP!, {LR}     }           /* Restore SPSR_irq to LR  */   \
  __asm { MSR     SPSR_cxsf, LR }           /* Copy LR to SPSR_irq     */   \

Reading from the Vector Interrupt Address Register,
VICVECTADDR, provides the address of the ISR, and updates the interrupt priority
hardware that masks out the current, and any lower priority interrupt requests. Writing
to the VICVECTADDR Register indicates to the interrupt priority hardware that the
current interrupt is serviced, enabling lower priority or the same priority interrupts to be
removed, and for the interrupts to become active to go active.

irq_handler:
/*- Manage Exception Entry */
/*- Adjust and save LR_irq in IRQ stack */
        sub      lr, lr, #4
        stmfd    sp!, {lr}
/*- Save r0 and SPSR in IRQ stack */
        mrs      r14, SPSR
        stmfd    sp!, {r0,r14}

/*- Write in the IVR to support Protect Mode */
/*- No effect in Normal Mode */
/*- De-assert the NIRQ and clear the source in Protect Mode */
        ldr      r14, =AT91C_BASE_AIC
        ldr      r0 , [r14, #AIC_IVR]
        str      r14, [r14, #AIC_IVR]

/*- Enable Interrupt and Switch in Supervisor Mode */
        msr      CPSR_c, #ARM_MODE_SVC

/*- Save scratch/used registers and LR in User Stack */
        stmfd    sp!, {r1-r3, r12, r14}

/*- Branch to the routine pointed by the AIC_IVR */
        mov      r14, pc
        bx       r0

/*- Restore scratch/used registers and LR from User Stack */
        ldmia    sp!, {r1-r3, r12, r14}

/*- Disable Interrupt and switch back in IRQ mode */
        msr      CPSR_c, #ARM_MODE_IRQ | I_BIT

/*- Mark the End of Interrupt on the AIC */
        ldr      r14, =AT91C_BASE_AIC
        str      r14, [r14, #AIC_EOICR]

/*- Restore SPSR_irq and r0 from IRQ stack */
        ldmia    sp!, {r0,r14}
        msr      SPSR_cxsf, r14

/*- Restore adjusted  LR_irq from IRQ stack directly in the PC */
        ldmia    sp!, {pc}^

__irq __nested __arm void irq_handler (void)
{
void (*interrupt_function)();
  unsigned int vector;
   vector = VICVectAddr;                   // Get interrupt vector.
   interrupt_function = (void(*)())vector; // Call MM_TIMER0_ISR thru pointer
  (*interrupt_function)();  // Call vectored interrupt function
  VICVectAddr = 0;          // Clear interrupt in VIC
}

void  MM_TIMER0_ISR()
{
   volatile unsigned int iPR;
  unsigned char PriA;
if(T0IR_bit.CR0INT)
  {
  
    TVK[0]++;
    if(VKN&0x01)
         {
           TCapi[0]=TCap[0];
           TCap[0] =T0CR0;
         }
    if(TVK[0]==1) VKN&=~0x01;
  T0IR_bit.CR0INT=1; // clear interrupt
  }
  
  // CAP_1
  if(T0IR_bit.CR1INT)
  {
    TVK[1]++;
    if (VKN&0x02)
    {
         TCapi[1]=TCap[1];
         TCap[1] =T0CR1;
    }
    if(TVK[1]==1) VKN&=~0x02;
   T0IR_bit.CR1INT=1;  // clear inteerupt
  }
  if(T0IR_bit.CR2INT)
  {  
     TVK[2]++;
    if (VKN&0x04)
    {
      TCapi[2]=TCap[2];
      TCap[2] =T0CR2;
    }
    if(TVK[2]==1) VKN&=~0x04;
  T0IR_bit.CR2INT=1;
  }
  
  if(T0IR_bit.CR3INT)
  {  
     TVK[3]++;
    if (VKN&0x08)
    {
      TCapi[3]=TCap[3];
      TCap[3] =T0CR3;
    }
    if(TVK[3]==1) VKN&=~0x08;
    T0IR_bit.CR3INT=1;
  }