#include <mega32.h>
#include <delay.h>
#include <string.h>
#include <stdlib.h>
#include <ctype.h>

  
#include "TI_CC_spi.h"
#include "TI_CC_spi.c"


void main ()
{
char str;

   TI_CC_SPISetup();                         // Initialize SPI port

       TI_CC_PowerupResetCCxxxx();               // Reset CCxxxx
       writeRFSettings();                        // Write RF settings to config reg
       TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE,paTable,paTableLen );//Write PATABLE  
       TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
       TI_CC_SPIStrobe(TI_CCxxx0_SFRX);
       TI_CC_SPIStrobe(TI_CCxxx0_SFTX);

str=TI_CC_SPIReadReg(TI_CCxxx0_PARTNUM);

lcd_str_ram(str,f8x14,red); // строки инициализации дисплея опущены.

}

#define mosi PORTB.5
#define miso PINB.6
#define sck PORTB.7
#define cs PORTB.1
#define gdo2 PIND.2
#define gdo0 PIND.3
#define light PORTD.4

// Configuration Registers
#define TI_CCxxx0_IOCFG2       0x00        // GDO2 output pin configuration
#define TI_CCxxx0_IOCFG1       0x01        // GDO1 output pin configuration
#define TI_CCxxx0_IOCFG0       0x02        // GDO0 output pin configuration
#define TI_CCxxx0_FIFOTHR      0x03        // RX FIFO and TX FIFO thresholds
#define TI_CCxxx0_SYNC1        0x04        // Sync word, high byte
#define TI_CCxxx0_SYNC0        0x05        // Sync word, low byte
#define TI_CCxxx0_PKTLEN       0x06        // Packet length
#define TI_CCxxx0_PKTCTRL1     0x07        // Packet automation control
#define TI_CCxxx0_PKTCTRL0     0x08        // Packet automation control
#define TI_CCxxx0_ADDR         0x09        // Device address
#define TI_CCxxx0_CHANNR       0x0A        // Channel number
#define TI_CCxxx0_FSCTRL1      0x0B        // Frequency synthesizer control
#define TI_CCxxx0_FSCTRL0      0x0C        // Frequency synthesizer control
#define TI_CCxxx0_FREQ2        0x0D        // Frequency control word, high byte
#define TI_CCxxx0_FREQ1        0x0E        // Frequency control word, middle byte
#define TI_CCxxx0_FREQ0        0x0F        // Frequency control word, low byte
#define TI_CCxxx0_MDMCFG4      0x10        // Modem configuration
#define TI_CCxxx0_MDMCFG3      0x11        // Modem configuration
#define TI_CCxxx0_MDMCFG2      0x12        // Modem configuration
#define TI_CCxxx0_MDMCFG1      0x13        // Modem configuration
#define TI_CCxxx0_MDMCFG0      0x14        // Modem configuration
#define TI_CCxxx0_DEVIATN      0x15        // Modem deviation setting
#define TI_CCxxx0_MCSM2        0x16        // Main Radio Cntrl State Machine config
#define TI_CCxxx0_MCSM1        0x17        // Main Radio Cntrl State Machine config
#define TI_CCxxx0_MCSM0        0x18        // Main Radio Cntrl State Machine config
#define TI_CCxxx0_FOCCFG       0x19        // Frequency Offset Compensation config
#define TI_CCxxx0_BSCFG        0x1A        // Bit Synchronization configuration
#define TI_CCxxx0_AGCCTRL2     0x1B        // AGC control
#define TI_CCxxx0_AGCCTRL1     0x1C        // AGC control
#define TI_CCxxx0_AGCCTRL0     0x1D        // AGC control
#define TI_CCxxx0_WOREVT1      0x1E        // High byte Event 0 timeout
#define TI_CCxxx0_WOREVT0      0x1F        // Low byte Event 0 timeout
#define TI_CCxxx0_WORCTRL      0x20        // Wake On Radio control
#define TI_CCxxx0_FREND1       0x21        // Front end RX configuration
#define TI_CCxxx0_FREND0       0x22        // Front end TX configuration
#define TI_CCxxx0_FSCAL3       0x23        // Frequency synthesizer calibration
#define TI_CCxxx0_FSCAL2       0x24        // Frequency synthesizer calibration
#define TI_CCxxx0_FSCAL1       0x25        // Frequency synthesizer calibration
#define TI_CCxxx0_FSCAL0       0x26        // Frequency synthesizer calibration
#define TI_CCxxx0_RCCTRL1      0x27        // RC oscillator configuration
#define TI_CCxxx0_RCCTRL0      0x28        // RC oscillator configuration
#define TI_CCxxx0_FSTEST       0x29        // Frequency synthesizer cal control
#define TI_CCxxx0_PTEST        0x2A        // Production test
#define TI_CCxxx0_AGCTEST      0x2B        // AGC test
#define TI_CCxxx0_TEST2        0x2C        // Various test settings
#define TI_CCxxx0_TEST1        0x2D        // Various test settings
#define TI_CCxxx0_TEST0        0x2E        // Various test settings

// Strobe commands
#define TI_CCxxx0_SRES         0x30        // Reset chip.
#define TI_CCxxx0_SFSTXON      0x31        // Enable/calibrate freq synthesizer
#define TI_CCxxx0_SXOFF        0x32        // Turn off crystal oscillator.
#define TI_CCxxx0_SCAL         0x33        // Calibrate freq synthesizer & disable
#define TI_CCxxx0_SRX          0x34        // Enable RX.
#define TI_CCxxx0_STX          0x35        // Enable TX.
#define TI_CCxxx0_SIDLE        0x36        // Exit RX / TX
#define TI_CCxxx0_SAFC         0x37        // AFC adjustment of freq synthesizer
#define TI_CCxxx0_SWOR         0x38        // Start automatic RX polling sequence
#define TI_CCxxx0_SPWD         0x39        // Enter pwr down mode when CSn goes hi
#define TI_CCxxx0_SFRX         0x3A        // Flush the RX FIFO buffer.
#define TI_CCxxx0_SFTX         0x3B        // Flush the TX FIFO buffer.
#define TI_CCxxx0_SWORRST      0x3C        // Reset real time clock.
#define TI_CCxxx0_SNOP         0x3D        // No operation.

// Status registers
#define TI_CCxxx0_PARTNUM      0x30        // Part number
#define TI_CCxxx0_VERSION      0x31        // Current version number
#define TI_CCxxx0_FREQEST      0x32        // Frequency offset estimate
#define TI_CCxxx0_LQI          0x33        // Demodulator estimate for link quality
#define TI_CCxxx0_RSSI         0x34        // Received signal strength indication
#define TI_CCxxx0_MARCSTATE    0x35        // Control state machine state
#define TI_CCxxx0_WORTIME1     0x36        // High byte of WOR timer
#define TI_CCxxx0_WORTIME0     0x37        // Low byte of WOR timer
#define TI_CCxxx0_PKTSTATUS    0x38        // Current GDOx status and packet status
#define TI_CCxxx0_VCO_VC_DAC   0x39        // Current setting from PLL cal module
#define TI_CCxxx0_TXBYTES      0x3A        // Underflow and # of bytes in TXFIFO
#define TI_CCxxx0_RXBYTES      0x3B        // Overflow and # of bytes in RXFIFO
#define TI_CCxxx0_NUM_RXBYTES  0x7F        // Mask "# of bytes" field in _RXBYTES

// Other memory locations
#define TI_CCxxx0_PATABLE      0x3E
#define TI_CCxxx0_TXFIFO       0x3F
#define TI_CCxxx0_RXFIFO       0x3F

// Masks for appended status bytes
#define TI_CCxxx0_LQI_RX       0x01        // Position of LQI byte
#define TI_CCxxx0_CRC_OK       0x80        // Mask "CRC_OK" bit within LQI byte

// Definitions to support burst/single access:
#define TI_CCxxx0_WRITE_BURST  0x40
#define TI_CCxxx0_READ_SINGLE  0x80
#define TI_CCxxx0_READ_BURST   0xC0



// PATABLE (0 dBm output power)
char paTable[] = {0xff};
char paTableLen = 1;


void TI_CC_SPISetup(void);
void TI_CC_PowerupResetCCxxxx(void);
void TI_CC_SPIWriteReg(char, char);
void TI_CC_SPIWriteBurstReg(char, char*, char);
char TI_CC_SPIReadReg(char);
void TI_CC_SPIReadBurstReg(char, char *, char);
char TI_CC_SPIReadStatus(char);
void TI_CC_SPIStrobe(char);
void RFSendPacket(char *txBuffer, char size);
void writeRFSettings(void);
char RFReceivePacket(char *rxBuffer, char *length);
void RF_TX_proc(void);
void RF_RX_proc(void);

void TI_CC_SPISetup(void)
{
    DDRB.5=1; // MOSI в out
    DDRB.1=1; // CS в out
    DDRB.6=0; // MISO в in
    DDRB.7=1; // SCK в out
    cs=1;
    sck=0;
    mosi=0;
}

// Output eight-bit value using selected bit-bang pins
void TI_CC_SPI_bitbang_out(char value)
{
  char x;

  for(x=8;x>0;x--){
    if(value & 0x80)mosi=1;                                    
    else mosi=0;
    #asm("nop")
    
    sck=1;
    value<<=1;
    #asm("nop")
    sck=0;
    #asm("nop")
    
    }
}

// Input eight-bit value using selected bit-bang pins
char TI_CC_SPI_bitbang_in()
{
  unsigned char x=0;
  unsigned char y;
        x=0;
  for(y=8;y>0;y--){
    sck=1;
    #asm("nop")
    x<<=1;
    if(miso==1){x|=0b00000001;}
    sck=0;
    #asm("nop")
    
    }                                         // Store next bit
  return(x);




}

void TI_CC_SPIWriteReg(char addr, char value)
{
    cs=0;                                   // /CS enable
    while (miso);                           // Wait CCxxxx ready
    TI_CC_SPI_bitbang_out(addr);            // Send address
    TI_CC_SPI_bitbang_out(value);           // Send data
    cs=1;                                   // /CS disable
}

void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
    char i;

    cs=0;                                   // /CS enable
    while (miso);                           // Wait CCxxxx ready
    TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_WRITE_BURST);   // Send address
    for (i = 0; i < count; i++)
      TI_CC_SPI_bitbang_out(buffer[i]);     // Send data
      cs=1;                                   // /CS disable
}

char TI_CC_SPIReadReg(char addr)
{
  char x;

  cs=0;
  while (miso);
  TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_READ_SINGLE);//Send address
  x = TI_CC_SPI_bitbang_in();               // Read data
  cs=1;                                   // /CS disable
  return x;
}

void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
  char i;
  cs=0;
  while (miso);
  TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_READ_BURST);    // Send address
  for (i = 0; i < count; i++){
    buffer[i] = TI_CC_SPI_bitbang_in();// Read data
    }    
  cs=1;                                   // /CS disable
  }

char TI_CC_SPIReadStatus(char addr)
{
  char x;
  cs=0;
  while (miso);                           // Wait CCxxxx ready                                   // /CS enable
  TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_READ_BURST);      // Send address
  x = TI_CC_SPI_bitbang_in();               // Read data
  cs=1;                                   // /CS disable
  return x;
}

void TI_CC_SPIStrobe(char strobe)
{
  cs=0;
  while (miso);                           // Wait CCxxxx ready                                   // /CS enable
  TI_CC_SPI_bitbang_out(strobe);            // Send strobe
  cs=1;                                   // /CS disable
}

void TI_CC_PowerupResetCCxxxx(void)
{
    cs=1;
    delay_us(40);
    cs=0;
    delay_us(40);
    cs=1;
    delay_us(45);
    cs=0;
    
    while(miso);
    TI_CC_SPI_bitbang_out(TI_CCxxx0_SRES);
    while(miso);
    cs=1;
    delay_ms(45);
    
}


// Chipcon
// Product = CC2500
// Chip version = E
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 551.067708 kHz
// Phase = 1
// Datarate = 250.240707 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2432.999988 MHz
// Channel spacing = 199.788952 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 1
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings

TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,0x0c);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,0x5B);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,0xFB);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,0x04);//04 rx    7c jeep
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,0x2d);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,0x36);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,0x73);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,0xc2);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,0xEF);
TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,0x01);
TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,0x56);
TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,0x10);
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2,0x07);
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1,0x3c);//30
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0,0x18);
TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,0x15);
TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,0x6C);
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2,0xc3);
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0,0x91);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,0xea);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,0x0A);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,0x11);
TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,0x59);
TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,0x8f);
TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,0x21);
TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,0x0B);
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,0x0F);
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,0x06);
TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1,0x0d);//05
TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0,0x05);
TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,0x01);
TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,0xff);
TI_CC_SPIWriteReg(TI_CCxxx0_FIFOTHR,0x07);

}