MODE/SYNC (Pin 7): Pulse Skip Mode Enable/Sync Pin. This multifunction pin provides pulse skip mode enable/
disable control and an external clock input to the phase detector. Pulling this pin below 0.8V or to an external
logic-level synchronization signal disables pulse skip mode operation and forces continuous operation. Pulling this
pin above 0.8V enables pulse skip mode operation. For a clock input, the phase-locked loop will force the rising top
gate signal to be synchronized with the rising edge of the clock signal.This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor to regulate a second output voltage.

25 , 26 выводы закоротите.