#include <atmel\ioat91sam7s256.h>
//инициализация основных узлов системы
void CPUinit()
  {
  //нициализация EFC (Flash-памяти)
  AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS; // 2 цикла на чтение, 3 цикла на запись
  //настройка тактовых частот
  //включение и задание времени запуска основного генератора
  AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
  // ожидание стабилизации частоты основного генератора
  while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
  
  //задание  частоты PLL  96,109 МГц и такт частоты UDP 48,058 МГц
  AT91C_BASE_PMC->PMC_PLLR =    (AT91C_CKGR_MUL & (72 << 16)) |
                                (AT91C_CKGR_DIV & 14);;
  //ожидание стабилизации PLL
  while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
    // ожидание стабилизации задающей частоты от PLL
  while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
  
  //задание задающей частоты и частоты процессора PLL/2=48 МГц
  //регистр PMC_MCKR не должен програмироваться одной операцией записи
  AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
  // ожидание стабилизации задающей частоты
  while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
  //выбор основного источника тактового сигнала PLL
  AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
  // ожидание стабилизации задающей частоты
  while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
  // отключение сторожевого таймера
  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
  
  // разрешение тактирования PIO
  AT91C_BASE_PMC->PMC_PCER|=(1 << AT91C_ID_PIOA);
  
  }
int main()
{
  CPUinit();
  AT91C_BASE_PIOA->PIO_PER=0xFFFFFFFF;
  AT91C_BASE_PIOA->PIO_OER=0xFFFFFFFF;
  AT91C_BASE_PIOA->PIO_CODR=0xFFFF0000;
  AT91C_BASE_PIOA->PIO_CODR=0x0000FFFF;
  
  return 0;
}

Wed Aug 26 14:51:09 2009: DLL version: V4.3o, compiled Feb 23 2009 18:04:20
Wed Aug 26 14:51:09 2009: Firmware: J-Link compiled Jul 30 2008 11:24:37 ARM Rev.5
Wed Aug 26 14:51:09 2009: JTAG speed is initially set to: 32 kHz
Wed Aug 26 14:51:09 2009: Initial reset was performed
Wed Aug 26 14:51:09 2009: TotalIRLen = 4, IRPrint = 0x01
Wed Aug 26 14:51:09 2009: J-Link found 1 JTAG device(s). ARM core Id: 3F0F0F0F ARM7
Wed Aug 26 14:51:09 2009: Device at TAP0 selected
Wed Aug 26 14:51:09 2009: JLINK command: ProjectFile = D:\PRUBORU\ARM ZAHUST\settings\DefenceOfGenerator_Debug.jlink, return = 0
Wed Aug 26 14:51:09 2009: JLINK command: device = AT91SAM7S256, return = 0
Wed Aug 26 14:51:09 2009: TotalIRLen = 4, IRPrint = 0x01
Wed Aug 26 14:51:09 2009: RTCK is not connected
Wed Aug 26 14:51:09 2009: Auto JTAG speed: 8000 kHz
Wed Aug 26 14:51:09 2009: 748 bytes downloaded (1.37 Kbytes/sec)
Wed Aug 26 14:51:09 2009: Loaded debugee: D:\PRUBORU\ARM ZAHUST\Debug\Exe\DefenceOfGenerator.out
Wed Aug 26 14:51:09 2009: Target reset
Wed Aug 26 14:51:10 2009: Failed to set breakpoint at 0x00000174
Wed Aug 26 14:51:10 2009: Failed to set breakpoint at 0x00000174
Wed Aug 26 14:51:59 2009: Failed to set breakpoint at 0x00000174
Wed Aug 26 14:51:59 2009: Performance warning: Lack of breakpoints forces single-stepping.

Wed Aug 26 15:06:40 2009: DLL version: V4.3o, compiled Feb 23 2009 18:04:20
Wed Aug 26 15:06:40 2009: Firmware: J-Link compiled Jul 30 2008 11:24:37 ARM Rev.5
Wed Aug 26 15:06:40 2009: JTAG speed is initially set to: 32 kHz
Wed Aug 26 15:06:40 2009: Initial reset was performed
Wed Aug 26 15:06:40 2009: TotalIRLen = 4, IRPrint = 0x01
Wed Aug 26 15:06:40 2009: J-Link found 1 JTAG device(s). ARM core Id: 3F0F0F0F ARM7
Wed Aug 26 15:06:40 2009: Device at TAP0 selected
Wed Aug 26 15:06:40 2009: JLINK command: ProjectFile = D:\PRUBORU\ARM ZAHUST\settings\DefenceOfGenerator_Debug.jlink, return = 0
Wed Aug 26 15:06:40 2009: JLINK command: device = AT91SAM7S256, return = 0
Wed Aug 26 15:06:40 2009: TotalIRLen = 4, IRPrint = 0x01
Wed Aug 26 15:06:40 2009: RTCK is not connected
Wed Aug 26 15:06:40 2009: Auto JTAG speed: 8000 kHz
Wed Aug 26 15:06:41 2009: 748 bytes downloaded (1.51 Kbytes/sec)
Wed Aug 26 15:06:41 2009: Loaded debugee: D:\PRUBORU\ARM ZAHUST\Debug\Exe\DefenceOfGenerator.out
Wed Aug 26 15:06:41 2009: Target reset
Wed Aug 26 15:06:46 2009: Failed to read one or more register values (busy).
Wed Aug 26 15:06:51 2009: The stack 'CSTACK' is filled to 100% (8192 bytes used out of 8192). The warning threshold is set to 90.%
Wed Aug 26 15:06:51 2009: The stack 'IRQ_STACK' is filled to 100% (256 bytes used out of 256). The warning threshold is set to 90.%
Wed Aug 26 15:06:51 2009: The stack 'FIQ_STACK' is filled to 100% (256 bytes used out of 256). The warning threshold is set to 90.%

  00100040  EAFFFFFE  B            0x100040
  00100044  EAFFFFFE  B            0x100044
  00100048  EAFFFFFE  B            0x100048
  [b]0010004C  EAFFFFFE  B            0x10004C[/b]
  00100050  EAFFFFFE  B            0x100050
  00100054  EAFFFFFE  B            0x100054
  00100058  E59F00C0  LDR          R0, [PC, #+192]        ; [0x100120] =RSTC_RCR (0xFFFFFD00)
  0010005C  E59F10C0  LDR          R1, [PC, #+192]        ; [0x100124] =0xA5000401
  00100060  E5801008  STR          R1, [R0, #+8]
  00100064  E3E000FF  MVN          R0, #0xFF
  00100068  E59F10B8  LDR          R1, [PC, #+184]        ; [0x100128] =0x320100
  0010006C  E5801060  STR          R1, [R0, #+96]
  00100070  E59F00B4  LDR          R0, [PC, #+180]        ; [0x10012C] =WDTC_WDCR (0xFFFFFD40)
  00100074  E3A01902  MOV          R1, #0x8000
  00100078  E5801004  STR          R1, [R0, #+4]
  0010007C  E59F00AC  LDR          R0, [PC, #+172]        ; [0x100130] =PMC_SCER (0xFFFFFC00)
  00100080  E59F10AC  LDR          R1, [PC, #+172]        ; [0x100134] =0x601
  00100084  E5801020  STR          R1, [R0, #+32]
  00100088  E5902068  LDR          R2, [R0, #+104]
  0010008C  E2122001  ANDS         R2, R2, #0x1

/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright © 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/

/*
IAR startup file for AT91SAM7S microcontrollers.
*/

MODULE ?cstartup

;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)

//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------

#define __ASSEMBLY__
#include "board.h"

//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------

#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F

#define I_BIT 0x80
#define F_BIT 0x40

//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------

/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)

PUBLIC resetVector
PUBLIC irqHandler

EXTERN Undefined_Handler
EXTERN SWI_Handler
EXTERN Prefetch_Handler
EXTERN Abort_Handler
EXTERN FIQ_Handler

ARM

__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done

resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR pc, =irqHandler ; IRQ
LDR pc, FIQ_Addr ; FIQ

Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
FIQ_Addr: DCD FIQ_Handler

/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
irqHandler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}

/* Write in the IVR to support Protect Mode */
LDR lr, =AT91C_BASE_AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]

/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SYS
STMFD sp!, {r1-r3, r4, r12, lr}
MOV lr, pc
BX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT

/* Acknowledge interrupt */
LDR lr, =AT91C_BASE_AIC
STR lr, [r14, #AIC_EOICR]

/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^


/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)

PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
ARM

resetHandler:

/* Set pc to actual code location (i.e. not in remap zone) */
LDR pc, =label

/* Perform low-level initialization of the chip using LowLevelInit() */
label:
LDR r0, =LowLevelInit
LDR r4, =SFE(CSTACK)
MOV sp, r4
MOV lr, pc
BX r0

/* Set up the interrupt stack pointer. */
MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
LDR sp, =SFE(IRQ_STACK)

/* Set up the SYS stack pointer. */
MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode
LDR sp, =SFE(CSTACK)

/* Branch to main() */
LDR r0, =?main
MOV lr, pc
BX r0

/* Loop indefinitely when program is finished */
loop4:
B loop4

END

#include "board.h"

[/code]
#include <atmel\ioat91sam7s256.h>
#include "at91sam7s256.h"

Warning[Lp012]: no sections with name FIQ_STACK included - special symbol FIQ_STACK$$Limit (referenced from cstartup.o(rt4t_al.a)) will be zero

Error[Li005]: no definition for "LowLevelInit" [referenced from D:\PRUBORU\ARM ZAHUST\DefenceOfGeneratorIAR\Release\Obj\boart_cstartup_iar.o]
Error while running Linker