module bin2bcd
(
clk ,
bin ,
bcd ,
enable_rd_bcd
);

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

input logic clk ;
input logic [12 : 0] bin ;
output logic [15 : 0] bcd ;
output logic enable_rd_bcd;

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
typedef logic [15:0] bcd_t;
typedef logic [12:0] bin_t;
typedef logic [3:0] dec_t;

dec_t ct_bit;
bin_t bin_rg;
bcd_t bcd_rg;

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

initial ct_bit = '0;

always_ff @ (posedge clk) begin
enable_rd_bcd <= (ct_bit == 0);
//
if (ct_bit == 0) begin
bcd <= bcd_rg;
bcd_rg <= '0;
bin_rg <= bin;
ct_bit <= 4'd13;
end
else begin
bcd_rg <= correct(bcd_rg, bin_rg[12]);
bin_rg <= (bin_rg << 1);
ct_bit <= ct_bit - 1'b1;
end
end

function automatic dec_t correct_decade ( input dec_t decade) ;
correct_decade = (decade > 4) ? (decade + 4'd3) : decade;
endfunction

function automatic bcd_t correct (input bcd_t data, input bit bitdata);
int i;
begin
for (i = 0; i < 4; i++)
correct [4*i +: 4] = correct_decade(data[4*i +: 4]);
correct = (correct << 1) | bitdata;
end
endfunction

endmodule