entity dualport_ram is
port (clk : in std_logic;
    memAWriteEnable : in std_logic;
    memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
    memAWrite : in std_logic_vector(wordSize-1 downto 0);
    memARead : out std_logic_vector(wordSize-1 downto 0);
    memBWriteEnable : in std_logic;
    memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
    memBWrite : in std_logic_vector(wordSize-1 downto 0);
    memBRead : out std_logic_vector(wordSize-1 downto 0));
end dualport_ram;

architecture dualport_ram_arch of dualport_ram is


type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);

shared variable ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80d5f40c",
3 => x"3a0b0b80",
4 => x"c4fb0400",



    others => x"00000000"
);

begin

process (clk)
begin
    if (clk'event and clk = '1') then
        if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
            report "write collision" severity failure;
        end if;
    
        if (memAWriteEnable = '1') then
            ram(to_integer(unsigned(memAAddr))) := memAWrite;
            memARead <= memAWrite;
        else
            memARead <= ram(to_integer(unsigned(memAAddr)));
        end if;
    end if;
end process;

process (clk)
begin
    if (clk'event and clk = '1') then
        if (memBWriteEnable = '1') then
            ram(to_integer(unsigned(memBAddr))) := memBWrite;
            memBRead <= memBWrite;
        else
            memBRead <= ram(to_integer(unsigned(memBAddr)));
        end if;
    end if;
end process;




end dualport_ram_arch;

Device Utilization Summary:

   Number of BUFGMUXs                        1 out of 8      12%
   Number of External IOBs                  91 out of 141    64%
      Number of LOCed IOBs                   0 out of 91      0%

   Number of RAMB16s                         8 out of 16     50%   - типа всё таки используется блочное ОЗУ для памяти
   Number of Slices                        312 out of 3584    8%
      Number of SLICEMs                      0 out of 1792    0%

0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80d5f40c",
3 => x"3a0b0b80",
4 => x"c4fb0400",

   RAMB16_S1_S1_inst : RAMB16_S1_S1
   generic map (
      INIT_A => "0", --  Value of output RAM registers on Port A at startup
      INIT_B => "0", --  Value of output RAM registers on Port B at startup
      SRVAL_A => "0", --  Port A ouput value upon SSR assertion
      SRVAL_B => "0", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Address 0 to 4095
      INIT_00 => X"1122330000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000....

если volatile unsigned char *p = (unsigned short *)(0xF000);
и      volatile unsigned char k;

то

00000541 <.LM7>:
k = *p;
541:    91              im 17
542:    d8              im -40
543:    08              load
544:    51              storesp 4
545:    70              loadsp 0
546:    33              loadb
547:    99              im 25
548:    8c              im 12
549:    34              storeb

0000054a <.LM8>:
p++;
54a:    81              im 1
54b:    11              addsp 4
54c:    91              im 17
54d:    d8              im -40
54e:    0c              store