always @(posedge CLK or negedge RESETn) begin
    if (!RESETn) begin
        State <= 0; SSP <= 1; TimerReg <= 0;
    end else begin
        if (Timer == 20'd0) begin
            case (State)
            0:    begin
                    SSP <= 1;
                    TimerReg <= 10;
                    State <= 1;
                end
            1:    begin
                    SSP <= 0;
                    TimerReg <= 2;
                    State <= 2;
                end
            2:    begin
                    SSP <= 1;
                    TimerReg <= 2;
                    State <= 3;
                end
            3:    begin
                    SSP <= 0;
                    TimerReg <= 3;
                    State <= 0;
                end
            endcase
        end
    end
end

always @(posedge CLK or negedge RESETn) begin
    if (!RESETn) begin
        Timer <= 0;
    end else begin
        if (Timer > 0) Timer <= Timer - 1'b1;
        else Timer <= TimerReg;
        
    end
end

wire DOUT;  // выход
//импульсы
wire [8:0] sample0 = 9'b100110011;
wire [2:0] sample1 = 3'b101;
......
wire [5:0] sample9 = 6'b110010;
//длины импульсов
wire [7:0] len0 = 8'h9, len1 = 8'h3, .. len9 = 8'h6;

reg [3:0] state;  //счетчик, номер последовательности
reg [7:0] count; //
reg [31:0] buf;  //стек для импульсов

always @(posedge clk or negedge resetn)
if(~resetn)
  begin
   state <= 4'h0;
   count <= 8'h0;
   buf[31:0] <= sample0;
  end
else
  begin
   if(state < 10)
   begin
    if(
       (state == 4'h0) & (count == len0) |
...
       (state == 4'h9) & (count == len9) )   //достигнут конец импульса
     begin
      state <= state + 1;       // смена номера импульса
      count <= 8'h0;             //обнуление указателя
      buf [31:0] <= ((state == 4'h0) & (count == len0)) ? sample0 :      //загрузка следющего ипульса
                             (((state == 4'h1) & (count == len1)) ? sample1 :
                                .........
                                sample9 ))))...))
     end
   else
    begin
     count <= count + 1;
     buf [31:0] <= buf [31:0] >> 1;  //сдвиг стека
    end
  end
else   state <= 4'h0; //полный цикл импульсов

assign DOUT = buf[0];