U-Boot 1.3.4 (Sep 24 2009 - 16:56:53)

DRAM: 64 MB
NAND: 256 MiB
DataFlash:AT45DB642
Nb pages: 8192
Page Size: 1056
Size= 8650752 bytes
Logical address: 0xC0000000
Area 0: C0000000 to C00041FF (RO) Bootstrap
Area 1: C0004200 to C00083FF Environment
Area 2: C0008400 to C0041FFF (RO) U-Boot
Area 3: C0042000 to C0251FFF Kernel
Area 4: C0252000 to C083FFFF FS
In: serial
Out: serial
Err: serial
Hit any key to stop autoboot: 0

NAND read: device 0 offset 0x200000, size 0x196cdc
1666268 bytes read: OK
## Booting kernel from Legacy Image at 22200000 ...
Image Name: linux-2.6
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 1666204 Bytes = 1.6 MB
Load Address: 20008000
Entry Point: 20008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux.............................................................
............................................ done, booting the kernel.
Linux version 2.6.30 (nferre@bendor) (gcc version 4.2.0 20070413 (prerelease) (C
odeSourcery Sourcery G++ Lite 2007q1-10)) #1 Mon Nov 2 17:07:10 CET 2009
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Atmel AT91SAM9RL-EK
Ignoring unrecognised tag 0x54410008
Memory policy: ECC disabled, Data cache writeback
Clocks: CPU 200 MHz, master 100 MHz, main 12.000 MHz
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
Kernel command line: mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfst
ype=jffs2
NR_IRQS:192
AT91: 128 gpio irqs in 4 banks
PID hash table entries: 256 (order: 8, 1024 bytes)
irq 1: nobody cared (try booting with the "irqpoll" option)
[<c00295a4>] (unwind_backtrace+0x0/0xdc) from [<c005c080>] (__report_bad_irq+0x3
0/0x88)
[<c005c080>] (__report_bad_irq+0x30/0x88) from [<c005c238>] (note_interrupt+0x16
0/0x1d4)
[<c005c238>] (note_interrupt+0x160/0x1d4) from [<c005cdc8>] (handle_level_irq+0x
90/0xf0)
[<c005cdc8>] (handle_level_irq+0x90/0xf0) from [<c0023050>] (_text+0x50/0x78)
[<c0023050>] (_text+0x50/0x78) from [<c0023994>] (__irq_svc+0x34/0x60)
Exception stack(0xc0315f08 to 0xc0315f50)
5f00: 00000001 c0314000 c033bde0 20000053 c0314000 00000000
5f20: 00000001 00000002 c033bde0 00000000 0000000a 00000000 00000005 c0315f50
5f40: c0023060 c003d81c 20000053 ffffffff
[<c0023994>] (__irq_svc+0x34/0x60) from [<c0023060>] (_text+0x60/0x78)
[<c0023060>] (_text+0x60/0x78) from [<00000001>] (0x1)
Exception stack(0xc0315f60 to 0xc0315fa8)
5f60: 00000000 00000001 c0317cd0 2001eb00 41069265 2001eacc 00000000 c0023060
5f80: 00000000 ffffffff fefff000 c0023994 00008001 00000000 00000001 20000053
5fa0: c0020eec c0337040
handlers:
[<c002df18>] (at91sam926x_pit_interrupt+0x0/0x70)
Disabling IRQ #1
Console: colour dummy device 80x30
console [ttyS0] enabled
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 61524KB available (2916K code, 221K data, 108K init, 0K highmem)
Calibrating delay loop...

/*
IAR startup file for AT91SAM9RL microcontrollers.
*/

MODULE ?cstartup

;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)

//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------

#define __ASSEMBLY__
#include "board.h"

//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------

#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F

#define I_BIT 0x80
#define F_BIT 0x40

//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------

/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)

PUBLIC resetVector
PUBLIC irqHandler

EXTERN Undefined_Handler
EXTERN SWI_Handler
EXTERN Prefetch_Handler
EXTERN Abort_Handler
EXTERN FIQ_Handler

ARM

__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done

resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR pc, =irqHandler ; IRQ
LDR pc, FIQ_Addr ; FIQ

Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
FIQ_Addr: DCD FIQ_Handler

/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
irqHandler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}

/* Write in the IVR to support Protect Mode */
LDR lr, =AT91C_BASE_AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]

/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SYS
STMFD sp!, {r1-r3, r4, r12, lr}
BLX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT

/* Acknowledge interrupt */
LDR lr, =AT91C_BASE_AIC
STR lr, [r14, #AIC_EOICR]

/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^


/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)

PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
ARM

resetHandler:

/* Set pc to actual code location (i.e. not in remap zone) */
LDR pc, =label

/* Perform low-level initialization of the chip using LowLevelInit() */
label:
LDR r0, =LowLevelInit
LDR r4, =SFE(CSTACK)
MOV sp, r4
BLX r0

/* Set up the interrupt stack pointer. */
MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
LDR sp, =SFE(IRQ_STACK)

/* Set up the SYS stack pointer. */
MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode
LDR sp, =SFE(CSTACK)

/* Branch to main() */
LDR r0, =?main
BLX r0

/* Loop indefinitely when program is finished */
loop4:
B loop4

END