Включение PLL
__disable_interrupt();



AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_MAIN_CLK;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );

AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 |
(16 << 8) |
(AT91C_CKGR_MUL & (72 << 16)) |
(AT91C_CKGR_DIV & 14);
// Wait for PLL stabilization
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
// Wait until the master clock is established for the case we already
// turn on the PLL
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );

AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );

AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
__enable_interrupt();
Выключение PLL
__disable_interrupt();
AT91F_PMC_CfgMCKReg (AT91C_BASE_PMC, AT91C_PMC_CSS_MAIN_CLK);
while(!(AT91F_PMC_GetStatus(AT91C_BASE_PMC) & AT91C_PMC_MCKRDY));
AT91F_CKGR_CfgPLLReg(AT91C_BASE_CKGR, 0);
__enable_interrupt();

AT91F_PMC_CfgMCKReg (AT91C_BASE_PMC, AT91C_PMC_CSS_MAIN_CLK);