module clock_switcher4clock
(
clkina ,
clkinb ,
clkinc ,
clkind ,
sel , // clkout = (sel == 0/1/2/3) -> clkina/clkinb/clkinc/clkind
clkout
);

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

input logic clkina;
input logic clkinb;
input logic clkinc;
input logic clkind;
input logic [1 : 0] sel ; // clkout = (sel == 0/1/2/3) -> clkina/clkinb/clkinc/clkind
output logic clkout;

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

logic ctrla;
logic ctrlb;
logic ctrlc;
logic ctrld;

logic [1:0] muxa;
logic [1:0] muxb;
logic [1:0] muxc;
logic [1:0] muxd;

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
// synthesis translate_off
initial begin : ini
muxa = '0;
muxb = '0;
muxc = '0;
muxd = '0;
end
// synthesis translate_on
//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

assign ctrla = ~sel[1] & ~sel[0] & ~muxb[1] & ~muxc[1] & ~muxd[1];
assign ctrlb = ~sel[1] & sel[0] & ~muxa[1] & ~muxc[1] & ~muxd[1];
assign ctrlc = sel[1] & ~sel[0] & ~muxa[1] & ~muxb[1] & ~muxd[1] ;
assign ctrld = sel[1] & sel[0] & ~muxa[1] & ~muxb[1] & ~muxc[1];


always_ff @(negedge clkina) begin
muxa <= {muxa[0], ctrla};
end

always_ff @(negedge clkinb) begin
muxb <= {muxb[0], ctrlb};
end

always_ff @(negedge clkinc) begin
muxc <= {muxc[0], ctrlc};
end

always_ff @(negedge clkind ) begin
muxd <= {muxd[0], ctrld};
end

assign clkout = (muxa[1] & clkina) | (muxb[1] & clkinb) | (muxc[1] & clkinc) | (muxd[1] & clkind);

endmodule

assign ctrla = ~sel & ~muxb[1];
assign ctrlb = sel & ~muxa[1];

always_ff @(negedge clkina) begin
muxa <= {muxa[0], ctrla};
end

always_ff @(negedge clkinb) begin
muxb <= {muxb[0], ctrlb};
end

assign clkout = (muxa[1] & clkina) | (muxb[1] & clkinb);

reg [1:0] clock_selector;
reg [1:0] loclk_dly;
reg [1:0] hiclk_dly;
reg [1:0] intclk_dly;

wire outclk;

always @(negedge lo_clk or posedge hw_reset)
  if (hw_reset) loclk_dly <= 2'b00; else
    loclk_dly <= {loclk_dly[0], (clock_selector == CK_LOW) && !hiclk_dly[1] && !intclk_dly[1] };

always @(negedge hi_clk or posedge hw_reset)
  if (hw_reset) hiclk_dly <= 2'b00; else
    hiclk_dly <= {hiclk_dly[0], (clock_selector == CK_HIGH) && !loclk_dly[1] && !intclk_dly[1] };

always @(negedge int_clk or posedge hw_reset)
  if (hw_reset) intclk_dly <= 2'b11; else
    intclk_dly <= {intclk_dly[0], ((clock_selector != CK_LOW) && (clock_selector != CK_HIGH)) && !hiclk_dly[1] && !loclk_dly[1] };

  wire tclk=(lo_clk & loclk_dly[1]) | (hi_clk & hiclk_dly[1]) | (int_clk & intclk_dly[1]);
  global gbl1 (.in(tclk), .out(outclk));

module clock_mux (clk,clk_select,clk_out);
parameter num_clocks = 4;
input [num_clocks-1:0] clk;
input [num_clocks-1:0] clk_select; // one hot
output clk_out;
genvar i;
reg [num_clocks-1:0] ena_r0;
reg [num_clocks-1:0] ena_r1;
reg [num_clocks-1:0] ena_r2;
wire [num_clocks-1:0] qualified_sel;
// A look-up-table (LUT) can glitch when multiple inputs
// change simultaneously. Use the keep attribute to
// insert a hard logic cell buffer and prevent
// the unrelated clocks from appearing on the same LUT.
wire [num_clocks-1:0] gated_clks /* synthesis keep */;
initial begin
ena_r0 = 0;
ena_r1 = 0;
ena_r2 = 0;
end
generate
for (i=0; i<num_clocks; i=i+1)
begin : lp0
wire [num_clocks-1:0] tmp_mask;
assign tmp_mask = {num_clocks{1'b1}} ^ (1 << i);
assign qualified_sel[i] = clk_select[i] &
(~|(ena_r2 & tmp_mask));
always @(posedge clk[i]) begin
ena_r0[i] <= qualified_sel[i];
ena_r1[i] <= ena_r0[i];
end
always @(negedge clk[i]) begin
ena_r2[i] <= ena_r1[i];
end
assign gated_clks[i] = clk[i] & ena_r2[i];
end
endgenerate
// These will not exhibit simultaneous toggle by construction
assign clk_out = |gated_clks;
endmodule

//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module switch_altclkctrl_9nd
(
clkselect,
ena,
inclk,
outclk) ;
input [1:0] clkselect;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] clkselect;
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

wire wire_clkctrl1_outclk;
wire [1:0] clkselect_wire;
wire [3:0] inclk_wire;

cycloneiii_clkctrl clkctrl1
(
.clkselect(clkselect_wire),
.ena(ena),
.inclk(inclk_wire),
.outclk(wire_clkctrl1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "cycloneiii_clkctrl";
assign
clkselect_wire = {clkselect},
inclk_wire = {inclk},
outclk = wire_clkctrl1_outclk;
endmodule //switch_altclkctrl_9nd
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module switch (
clkselect,
inclk0x,
inclk1x,
inclk2x,
inclk3x,
outclk);

input [1:0] clkselect;
input inclk0x;
input inclk1x;
input inclk2x;
input inclk3x;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] clkselect;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

wire sub_wire0;
wire sub_wire1 = 1'h1;
wire sub_wire6 = inclk3x;
wire sub_wire5 = inclk2x;
wire sub_wire4 = inclk0x;
wire outclk = sub_wire0;
wire sub_wire2 = inclk1x;
wire [3:0] sub_wire3 = {sub_wire6, sub_wire5, sub_wire2, sub_wire4};

switch_altclkctrl_9nd switch_altclkctrl_9nd_component (
.ena (sub_wire1),
.inclk (sub_wire3),
.clkselect (clkselect),
.outclk (sub_wire0));

endmodule

assign gated_clks[i] = clk[i] | ena_r2[i];

assign clk_out = &gated_clks;