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PCI Express board on Spartan 3 or Virtex 2 pro |
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Dec 30 2005, 05:55
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Hi, Anyone has developed PCI Express Board (x1 or x4 link) on spartan 3 or Virtex2pro? I want to develop this board, x1 link, 256MB DDR II SSDRAM, USB2.0 controller, 2 Spartan3 2000 or VirtexIIpro 50, 10/100/1G ethernet PHY, Audio processing. Can anyone be interested in doing this project? PM me
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Dec 30 2005, 06:31
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Цитата(keshu @ Dec 30 2005, 00:55)  Hi, Anyone has developed PCI Express Board (x1 or x4 link) on spartan 3 or Virtex2pro? I want to develop this board, x1 link, 256MB DDR II SSDRAM, USB2.0 controller, 2 Spartan3 2000 or VirtexIIpro 50, 10/100/1G ethernet PHY, Audio processing. Can anyone be interested in doing this project? PM me  Good day! My english is'not very well, I hope you can understand me IMHO PCI-E is imposible to made base'd on Spartan 3 only, becouse as far as I know there is not SERDES block's. It can be maded based on Virtex2pro, Virtex4FX, or using special PCI-X bridge. if you find outsorces developer for you project, i have great interest about video/audio processing. I'd like to be in groop of developer's for dooing this project But I need time to think have i enouth time o not.  ( You can find me by forum's mail. truly yours des00
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Dec 30 2005, 22:55
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I designed 1x/2x/4x lanes PCI-Express controller on Virtex 2 Pro , it will be soon tested for compatibility with PCI-Express on PC motherboard.
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Jan 2 2006, 08:24
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des00,
True, you are right that I need to have a SerDes block (or PMA). For that I plan to make use of Philips x1 standalone PIPE compliant PHY ASIC.
link: can you share few of your project high lights with all of us.
Thanks, Keshu
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Jan 4 2006, 06:39
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Unfortunately I can't share sources of the designed core, i just can help in some questions while designing.
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Jan 5 2006, 13:33
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Hi Link,
I have following questions regarding design 1. What is the data path width? and the frequency of operation of your core? 2. Can you core which is actually configured as x4 work well if placed in x1 slot. That is will it behave as x1? 3. How have you implemented the LTSSM module? 4. How is scrambler/descrambler implemented? 5. What are the memory used in your core. 6. Do you core implements ASPM and PCI PM 7. You are putting your core on Virtex II, now Rocket IO does not support electrical Idle signal, becaon, lane to lane deskew. How have to taken care in your design abt this?
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Feb 10 2006, 09:41
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2 Keshu
1. 64 bit internal data path, frequency depends on lane number. 125 MHz for 4-lane, 62.5 MHz - for 2 lane, 31.25 - for 1 lane mode.
2. Yes. 3. 4. It's difficult to describe by words. Maybe you mean something concrete ? 5. V2Pro Dual Port BlockRAM components. 6. No 7. lane to lane deskew supported. The other does not.
Xilinx has it's logical core based on V2Pro, so they say it's compatible with PCI-Express specification.
2 alex_k Ядру еще предстоит пройти проверку на совместимость стандарту, в том числе в режимах 1x, 4x, если удасться то 2x, и т.д. Соответственно модели в течении какого-то времени будут меняться. Пока ядро работает в режиме 1x. Если по прежнему интересует приобретение ядра, могу связаться с начальством по этому вопросу..
Сообщение отредактировал Link - Feb 10 2006, 09:47
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